{"id":"https://openalex.org/W2162208141","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212619","title":"An efficient memory controller for 3D heterogeneous integration platform","display_name":"An efficient memory controller for 3D heterogeneous integration platform","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2162208141","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212619","mag":"2162208141"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212619","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212619","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Yi-Jun Liu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yi-Jun Liu","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039735116","display_name":"Chih-Chyau Yang","orcid":"https://orcid.org/0000-0001-6508-8160"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chih-Chyau Yang","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025762419","display_name":"Shih\u2010Lun Chen","orcid":"https://orcid.org/0000-0002-4079-9350"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Shih-Lun Chen","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071430405","display_name":"Chun\u2010Chieh Chiu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Chieh Chiu","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012979818","display_name":"Chun-Chieh Chu","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Chieh Chu","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103047746","display_name":"Chien\u2010Ming Wu","orcid":"https://orcid.org/0000-0001-9295-7181"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chien-Ming Wu","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101901556","display_name":"Chun-Ming Huang","orcid":"https://orcid.org/0000-0001-7973-9112"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chun-Ming Huang","raw_affiliation_strings":["National Chip Implementation Center, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Chip Implementation Center, Hsinchu, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3726,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6786252,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7201720476150513},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6772857904434204},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.5846614241600037},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.5779097080230713},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5621985793113708},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5301923155784607},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5231867432594299},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.48604923486709595},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.45037543773651123},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.41617459058761597},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4113156795501709},{"id":"https://openalex.org/keywords/computer-data-storage","display_name":"Computer data storage","score":0.3336346745491028},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3215028643608093},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3181770443916321},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.18119388818740845},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11459174752235413}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7201720476150513},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6772857904434204},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.5846614241600037},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.5779097080230713},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5621985793113708},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5301923155784607},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5231867432594299},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.48604923486709595},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.45037543773651123},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.41617459058761597},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4113156795501709},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.3336346745491028},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3215028643608093},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3181770443916321},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.18119388818740845},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11459174752235413},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212619","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212619","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7400000095367432}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2073906129","https://openalex.org/W2104315811","https://openalex.org/W2118339691","https://openalex.org/W2144331304","https://openalex.org/W2144641451"],"related_works":["https://openalex.org/W4242495027","https://openalex.org/W2019238062","https://openalex.org/W3049130895","https://openalex.org/W773491645","https://openalex.org/W4285245242","https://openalex.org/W2100773763","https://openalex.org/W2898989424","https://openalex.org/W4285257158","https://openalex.org/W3093911585","https://openalex.org/W2376756065"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"efficient":[4],"memory":[5,43,48,57,66,87,92,104,144,176],"controller":[6,49,58,88],"VLSI":[7],"design":[8],"for":[9,76],"integrating":[10],"a":[11,20,45,68],"3D":[12],"heterogeneous":[13,30],"MorPACK":[14,17,74],"system.":[15],"The":[16,55,138],"system":[18,23],"is":[19,27,50,146],"platform-based":[21],"integration":[22],"and":[24,38,64],"its":[25],"structure":[26],"stacked":[28],"by":[29,82,130],"sub-modules.":[31],"In":[32],"order":[33],"to":[34,89],"reduce":[35,121,128],"fabrication":[36,186],"cost":[37,187],"increase":[39],"the":[40,84,96,99,110,117,124,132,153,164,178],"flexibility":[41],"of":[42,98,112,134,142,172],"extension,":[44],"novel":[46],"multimode":[47,56],"proposed":[51,100,174],"in":[52,152],"this":[53],"paper.":[54],"supports":[59],"NOR":[60],"flash,":[61,63],"NAND":[62],"SDRAM":[65],"with":[67,163],"wide":[69],"capacity":[70],"range.":[71],"Hence,":[72],"different":[73,91],"systems":[75],"various":[77],"applications":[78],"can":[79,120,127],"be":[80],"integrated":[81],"using":[83],"same":[85],"multi-mode":[86,175],"satisfy":[90],"requirements.":[93],"To":[94],"demonstrate":[95],"effectiveness":[97],"methodology,":[101],"three":[102],"single-mode":[103,143],"controllers":[105,145],"are":[106,183],"also":[107],"implemented.":[108],"With":[109],"technique":[111,133],"sharing":[113,135],"one":[114],"system-side":[115],"signals,":[116],"pin":[118,125],"count":[119,126],"41.9%":[122],"while":[123],"19.2%":[129],"applying":[131],"memory-side":[136],"signals.":[137],"total":[139,165],"silicon":[140],"area":[141,167],"about":[147],"6.83-mm":[148],"<sup":[149,169],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[150,170],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[151,171],"TSMC":[154],"90":[155],"nm":[156],"CMOS":[157],"generic":[158],"logic":[159],"process":[160],"technology.":[161],"Compared":[162],"chip":[166],"3.1-mm":[168],"our":[173],"controller,":[177],"results":[179],"show":[180],"that":[181],"there":[182],"54.7":[184],"%":[185],"reduced.":[188]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
