{"id":"https://openalex.org/W2037136790","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212599","title":"Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm","display_name":"Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm","publication_year":2012,"publication_date":"2012-04-01","ids":{"openalex":"https://openalex.org/W2037136790","doi":"https://doi.org/10.1109/vlsi-dat.2012.6212599","mag":"2037136790"},"language":"en","primary_location":{"id":"doi:10.1109/vlsi-dat.2012.6212599","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212599","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030855035","display_name":"M. N. Chowdhury","orcid":"https://orcid.org/0000-0003-3577-9395"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"N. Chowdhury","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113028165","display_name":"J. Wight","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Wight","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076645571","display_name":"Christopher Mozak","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Mozak","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034919212","display_name":"Nasser Kurd","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Kurd","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, 2111 NE 25th Ave, Hillsboro, Oregon 97124, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5030855035"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.2455,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59092133,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.7613444328308105},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6416346430778503},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.5309851765632629},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4623286724090576},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4560125470161438},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43454331159591675},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3275284171104431},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2420421838760376},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24071276187896729},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15930867195129395},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09844663739204407}],"concepts":[{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.7613444328308105},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6416346430778503},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.5309851765632629},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4623286724090576},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4560125470161438},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43454331159591675},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3275284171104431},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2420421838760376},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24071276187896729},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15930867195129395},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09844663739204407},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsi-dat.2012.6212599","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsi-dat.2012.6212599","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Technical Program of 2012 VLSI Design, Automation and Test","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6100000143051147,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2051846227","https://openalex.org/W2053362661","https://openalex.org/W2080418535","https://openalex.org/W2082715750","https://openalex.org/W6670984688"],"related_works":["https://openalex.org/W2361454123","https://openalex.org/W2385247776","https://openalex.org/W2127916158","https://openalex.org/W2100196563","https://openalex.org/W2106546050","https://openalex.org/W1553497204","https://openalex.org/W2382142327","https://openalex.org/W2977359002","https://openalex.org/W2598933208","https://openalex.org/W2532282409"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,93,101,106],"forwarded":[4],"clock":[5],"amplifier":[6],"(FCA),":[7],"phase":[8],"interpolator":[9],"(PI)":[10],"and":[11,29,40,74,81],"training":[12,80],"algorithm":[13,83],"used":[14,35,63],"in":[15,22,27,55],"receiver":[16,66],"clocking":[17],"of":[18,100],"QuickPath":[19],"Interconnect\u2122":[20],"(QPI)":[21],"Intel\u00ae":[23],"Core\u2122":[24],"micro-processor,":[25],"implemented":[26],"45nm":[28],"32nm":[30],"process":[31],"technologies.":[32],"QPI":[33],"is":[34],"for":[36,64,87,95],"communication":[37],"among":[38],"processors/chipsets":[39],"delivers":[41],"up":[42],"to":[43,68,71],"25.6GB/s":[44],"BW":[45],"per":[46],"port":[47],"at":[48],"6.4GT/s.":[49],"The":[50,78],"FCA":[51],"has":[52],"a":[53],"built":[54],"duty":[56,97],"cycle":[57,98],"corrector":[58],"(DCC).":[59],"Two":[60],"PIs":[61],"were":[62],"each":[65,85],"lane":[67],"generate":[69],"clocks":[70],"capture":[72],"odd":[73],"even":[75],"data":[76,90],"independently.":[77],"novel":[79],"retraining":[82],"trains":[84],"PI":[86,102],"its":[88],"corresponding":[89],"eye":[91,107],"eliminating":[92],"need":[94],"any":[96],"correction":[99],"output":[103],"while":[104],"maximizing":[105],"margin.":[108]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}