{"id":"https://openalex.org/W2012721802","doi":"https://doi.org/10.1109/vldi-dat.2013.6533870","title":"A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism","display_name":"A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2012721802","doi":"https://doi.org/10.1109/vldi-dat.2013.6533870","mag":"2012721802"},"language":"en","primary_location":{"id":"doi:10.1109/vldi-dat.2013.6533870","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vldi-dat.2013.6533870","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101721828","display_name":"Chia-Yu Yao","orcid":"https://orcid.org/0000-0001-9771-041X"},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Yu Yao","raw_affiliation_strings":["Department of Electrical Engineering, NTUST, Taipei, Taiwan","[Dept. of Electr. Eng., NTUST, Taipei, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, NTUST, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., NTUST, Taipei, Taiwan]","institution_ids":["https://openalex.org/I154864474"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062367921","display_name":"Yung-Hsiang Ho","orcid":null},"institutions":[{"id":"https://openalex.org/I154864474","display_name":"National Taiwan University of Science and Technology","ror":"https://ror.org/00q09pe49","country_code":"TW","type":"education","lineage":["https://openalex.org/I154864474"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Hsiang Ho","raw_affiliation_strings":["Department of Electrical Engineering, NTUST, Taipei, Taiwan","[Dept. of Electr. Eng., NTUST, Taipei, Taiwan]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, NTUST, Taipei, Taiwan","institution_ids":["https://openalex.org/I154864474"]},{"raw_affiliation_string":"[Dept. of Electr. Eng., NTUST, Taipei, Taiwan]","institution_ids":["https://openalex.org/I154864474"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I154864474"],"apc_list":null,"apc_paid":null,"fwci":1.2159,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.75144169,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"2","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6953123807907104},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.6672285795211792},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6649959683418274},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5947684645652771},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.5883893966674805},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.554542064666748},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5497187376022339},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5376964807510376},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5262300968170166},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4898059070110321},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.48670127987861633},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4183051586151123},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.38914021849632263},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18361592292785645},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13087323307991028}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6953123807907104},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.6672285795211792},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6649959683418274},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5947684645652771},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.5883893966674805},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.554542064666748},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5497187376022339},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5376964807510376},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5262300968170166},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4898059070110321},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.48670127987861633},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4183051586151123},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.38914021849632263},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18361592292785645},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13087323307991028},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vldi-dat.2013.6533870","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vldi-dat.2013.6533870","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1790800520","https://openalex.org/W1997826936","https://openalex.org/W2002187871","https://openalex.org/W2009275112","https://openalex.org/W2018092108","https://openalex.org/W2019109746","https://openalex.org/W2111053525","https://openalex.org/W2117599119","https://openalex.org/W2124390946","https://openalex.org/W2126227985","https://openalex.org/W2133294020","https://openalex.org/W2141594064","https://openalex.org/W2143232235","https://openalex.org/W2143738690","https://openalex.org/W2144572765","https://openalex.org/W6638299517","https://openalex.org/W6655305116"],"related_works":["https://openalex.org/W2052455055","https://openalex.org/W2133326759","https://openalex.org/W2174922170","https://openalex.org/W3006003651","https://openalex.org/W2169622190","https://openalex.org/W2001020839","https://openalex.org/W4386968318","https://openalex.org/W1506442459","https://openalex.org/W2285301449","https://openalex.org/W1490033429"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"11-bit":[4],"all-digital":[5],"delay-locked":[6],"loop":[7],"(ADDLL)":[8],"with":[9],"a":[10,20,29,57,75],"starting":[11,78],"SAR-bit":[12],"prediction":[13],"(SSARBP)":[14],"mechanism.":[15],"The":[16,85,97,139],"proposed":[17,38,103],"circuit":[18,61,104],"possesses":[19],"wide-operating":[21],"range":[22],"such":[23],"that":[24,101],"it":[25],"can":[26,43,48,105],"serve":[27],"as":[28],"de-skew":[30],"buffer":[31],"for":[32],"the":[33,37,41,50,54,60,63,67,82,102,114,118,127,131,143],"clock":[34,124,137,157],"signal.":[35],"With":[36],"SSARBP":[39,58],"mechanism,":[40],"ADDLL":[42,86],"achieve":[44],"fast":[45],"lock":[46,83,119,132],"and":[47,155],"eliminate":[49],"harmonic":[51],"lock.":[52],"In":[53,113,126],"beginning":[55],"of":[56,66,142],"cycle,":[59],"estimates":[62],"current":[64],"delay":[65,69],"digital-controlled":[68],"line":[70],"(DCDL).":[71],"We":[72],"then":[73],"predict":[74],"suitable":[76],"SAR":[77],"bit":[79],"to":[80,110,147],"shorten":[81],"time.":[84],"chip":[87,144],"is":[88,121,134,145],"designed":[89],"using":[90],"TSMC's":[91],"0.18":[92],"\u03bcm":[93],"CMOS":[94],"cell":[95],"library.":[96],"post-simulation":[98],"results":[99],"show":[100],"operate":[106],"from":[107],"66":[108],"MHz":[109],"1":[111],"GHz.":[112],"low":[115],"frequency":[116,129],"band,":[117,130],"time":[120,133],"within":[122,135],"17-23":[123],"cycles.":[125,138],"high":[128],"17-32":[136],"power":[140],"consumption":[141],"estimated":[146],"be":[148],"22":[149],"mW":[150],"at":[151],"1.8-V":[152],"supply":[153],"voltage":[154],"1-GHz":[156],"frequency.":[158]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
