{"id":"https://openalex.org/W2038193917","doi":"https://doi.org/10.1109/vldi-dat.2013.6533820","title":"A layout-aware automatic sizing approach for retargeting analog integrated circuits","display_name":"A layout-aware automatic sizing approach for retargeting analog integrated circuits","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W2038193917","doi":"https://doi.org/10.1109/vldi-dat.2013.6533820","mag":"2038193917"},"language":"en","primary_location":{"id":"doi:10.1109/vldi-dat.2013.6533820","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vldi-dat.2013.6533820","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006232460","display_name":"Yen\u2010Lung Chen","orcid":"https://orcid.org/0000-0003-1580-9139"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen-Lung Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jung Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jung Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100856581","display_name":"Yi-Ching Ding","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Ching Ding","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jung Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jung Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038997887","display_name":"Yu-Ching Liao","orcid":"https://orcid.org/0000-0002-4575-6018"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Ching Liao","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jung Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jung Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018644771","display_name":"Hsin-Ju Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsin-Ju Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jung Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jung Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048544383","display_name":"C-N J. Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"C-N J. Liu","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Jung Li, Taiwan","Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Jung Li, Taiwan","institution_ids":["https://openalex.org/I22265921"]},{"raw_affiliation_string":"Dept. of Electr. Eng., National Central Univ., Jungli, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9602,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.78701804,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retargeting","display_name":"Retargeting","score":0.9496094584465027},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7759727239608765},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.711097002029419},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.6588218808174133},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6439819931983948},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.6417754292488098},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.614655613899231},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5900335907936096},{"id":"https://openalex.org/keywords/seam-carving","display_name":"Seam carving","score":0.5737523436546326},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5646883845329285},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.45342162251472473},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4441715478897095},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4155203700065613},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3551729619503021},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.3480493724346161},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.33787333965301514},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.31467562913894653},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24961727857589722},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.22468894720077515},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20922958850860596},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10355129837989807},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09824955463409424}],"concepts":[{"id":"https://openalex.org/C2780575108","wikidata":"https://www.wikidata.org/wiki/Q7316652","display_name":"Retargeting","level":2,"score":0.9496094584465027},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7759727239608765},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.711097002029419},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.6588218808174133},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6439819931983948},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.6417754292488098},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.614655613899231},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5900335907936096},{"id":"https://openalex.org/C23746413","wikidata":"https://www.wikidata.org/wiki/Q1141379","display_name":"Seam carving","level":3,"score":0.5737523436546326},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5646883845329285},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.45342162251472473},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4441715478897095},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4155203700065613},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3551729619503021},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.3480493724346161},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.33787333965301514},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.31467562913894653},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24961727857589722},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.22468894720077515},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20922958850860596},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10355129837989807},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09824955463409424},{"id":"https://openalex.org/C160633673","wikidata":"https://www.wikidata.org/wiki/Q355198","display_name":"Pixel","level":2,"score":0.0},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vldi-dat.2013.6533820","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vldi-dat.2013.6533820","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1831130662","https://openalex.org/W1872183006","https://openalex.org/W1998752433","https://openalex.org/W2007513980","https://openalex.org/W2039300364","https://openalex.org/W2099802145","https://openalex.org/W2106476087","https://openalex.org/W2111776955","https://openalex.org/W2116989584","https://openalex.org/W2136848459","https://openalex.org/W2144133630","https://openalex.org/W2149029467","https://openalex.org/W2152293425","https://openalex.org/W2156995134","https://openalex.org/W2166282246","https://openalex.org/W2166359146","https://openalex.org/W4230336076","https://openalex.org/W4238577093","https://openalex.org/W6638598875","https://openalex.org/W6652144651","https://openalex.org/W6682627371","https://openalex.org/W6683136492"],"related_works":["https://openalex.org/W2123992435","https://openalex.org/W2091329789","https://openalex.org/W1993861866","https://openalex.org/W4244378213","https://openalex.org/W1605062719","https://openalex.org/W2141750279","https://openalex.org/W2149029467","https://openalex.org/W2038193917","https://openalex.org/W2162651506","https://openalex.org/W2904595763"],"abstract_inverted_index":{"Automatically":[0],"retargeting":[1,23,62,130],"analog":[2,13,63],"designs":[3],"to":[4,26,51],"new":[5,29,85],"technology":[6,34,86],"is":[7,35,65],"an":[8],"efficient":[9],"solution":[10],"for":[11,32,61],"reusing":[12],"IPs.":[14],"However,":[15],"most":[16],"of":[17,148],"previous":[18],"approaches":[19],"focus":[20],"on":[21,71],"layout":[22,73],"only.":[24],"How":[25],"obtain":[27],"the":[28,41,47,52,72,77,80,91,95,112,119,125,128,139,144],"device":[30,42],"sizes":[31,43],"another":[33],"often":[36],"not":[37,45],"discussed.":[38],"Simply":[39],"scaling":[40],"may":[44],"reach":[46],"desired":[48],"performance":[49,97],"due":[50],"non-ideal":[53],"effects.":[54],"Therefore,":[55],"a":[56],"layout-aware":[57],"automatic":[58],"sizing":[59,92,114],"flow":[60],"circuits":[64],"proposed":[66,113,140],"in":[67,84,90,111,124,134],"this":[68,149],"paper.":[69],"Based":[70],"template":[74],"extracted":[75],"from":[76],"original":[78],"design,":[79],"layout-induced":[81],"parasitic":[82],"effects":[83],"are":[87,109],"also":[88],"considered":[89],"flow.":[93],"Since":[94],"possible":[96],"degradation":[98],"has":[99],"been":[100],"considered,":[101],"no":[102],"redesign":[103],"cycles":[104],"and":[105,146],"reserved":[106],"design":[107,120,129],"margins":[108],"required":[110],"flow,":[115,141],"which":[116,142],"significantly":[117],"reduces":[118],"overhead.":[121],"As":[122],"shown":[123],"experimental":[126],"results,":[127],"can":[131],"be":[132],"finished":[133],"one":[135],"second":[136],"by":[137],"using":[138],"demonstrates":[143],"feasibility":[145],"efficiency":[147],"approach.":[150]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
