{"id":"https://openalex.org/W1992098392","doi":"https://doi.org/10.1109/vldi-dat.2013.6533808","title":"An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages","display_name":"An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages","publication_year":2013,"publication_date":"2013-04-01","ids":{"openalex":"https://openalex.org/W1992098392","doi":"https://doi.org/10.1109/vldi-dat.2013.6533808","mag":"1992098392"},"language":"en","primary_location":{"id":"doi:10.1109/vldi-dat.2013.6533808","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vldi-dat.2013.6533808","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109935060","display_name":"Shin Abe","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"S. Abe","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056061175","display_name":"Youhua Shi","orcid":"https://orcid.org/0000-0002-1473-9776"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Youhua Shi","raw_affiliation_strings":["Waseda Institute for Advanced Study, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Waseda Institute for Advanced Study, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030692253","display_name":"Kimiyoshi Usami","orcid":"https://orcid.org/0000-0002-8911-3313"},"institutions":[{"id":"https://openalex.org/I171481255","display_name":"Shibaura Institute of Technology","ror":"https://ror.org/020wjcq07","country_code":"JP","type":"education","lineage":["https://openalex.org/I171481255"]},{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Usami","raw_affiliation_strings":["Department of Computer Science and Engineering, Department of Electronic and Photonic Systems, Waseda University, Japan","Department of Information Science and Engineering, Shibaura Institute of Technology, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Department of Electronic and Photonic Systems, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Department of Information Science and Engineering, Shibaura Institute of Technology, Japan","institution_ids":["https://openalex.org/I171481255"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061982025","display_name":"Masao Yanagisawa","orcid":"https://orcid.org/0000-0002-5168-3214"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Yanagisawa","raw_affiliation_strings":["Department of Computer Science and Engineering, Department of Electronic and Photonic Systems, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Department of Electronic and Photonic Systems, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087516286","display_name":"Nozomu Togawa","orcid":"https://orcid.org/0000-0003-3400-3587"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Togawa","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5109935060"],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06838675,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.820766806602478},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7655568718910217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6675799489021301},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.6009560823440552},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5946207046508789},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5249409675598145},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4460490643978119},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43802374601364136},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43566447496414185},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2838304340839386},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19845998287200928},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.18950408697128296},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11753058433532715},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.0908922553062439},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08535704016685486}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.820766806602478},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7655568718910217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6675799489021301},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6009560823440552},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5946207046508789},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5249409675598145},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4460490643978119},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43802374601364136},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43566447496414185},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2838304340839386},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19845998287200928},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.18950408697128296},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11753058433532715},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0908922553062439},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08535704016685486},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vldi-dat.2013.6533808","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vldi-dat.2013.6533808","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2003610890","https://openalex.org/W2005852288","https://openalex.org/W2007252437","https://openalex.org/W2013956913","https://openalex.org/W2037224163","https://openalex.org/W2133630856","https://openalex.org/W2137880600","https://openalex.org/W2143482204","https://openalex.org/W2151929849","https://openalex.org/W2158566102","https://openalex.org/W2159142998","https://openalex.org/W3140174600","https://openalex.org/W6681203127"],"related_works":["https://openalex.org/W2055008360","https://openalex.org/W1500063550","https://openalex.org/W2261987718","https://openalex.org/W3141861494","https://openalex.org/W2161004825","https://openalex.org/W2080729117","https://openalex.org/W2044534563","https://openalex.org/W1516038830","https://openalex.org/W2139708877","https://openalex.org/W1624807520"],"abstract_inverted_index":{"In":[0,46],"this":[1],"paper,":[2],"we":[3,26],"propose":[4,27],"an":[5],"adaptive":[6],"voltage":[7],"huddle-based":[8],"distributed-register":[9],"architecture":[10],"(AVHDR":[11],"architecture)":[12],"that":[13,93],"integrates":[14],"dynamic":[15],"multiple":[16],"supply":[17,84],"voltages":[18,67],"and":[19,44,73],"interconnection":[20],"delays":[21],"into":[22],"high-level":[23,29],"synthesis.":[24],"Next,":[25],"a":[28],"synthesis":[30],"algorithm":[31,36,95],"for":[32],"AVHDR":[33],"architectures.":[34],"Our":[35],"is":[37,76],"based":[38],"on":[39],"iterative":[40],"improvement":[41],"of":[42,52],"scheduling/binding":[43],"floorplanning.":[45,65],"the":[47,82,86],"iteration":[48],"process,":[49],"huddles,":[50],"each":[51,59],"which":[53],"abstracts":[54],"modules":[55],"placed":[56],"close":[57],"to":[58,70,85],"other,":[60],"are":[61,68],"naturally":[62],"generated":[63],"using":[64],"Low-supply":[66],"assigned":[69],"non-critical":[71],"operations,":[72],"leakage":[74],"power":[75,83],"cut":[77],"off":[78,81],"by":[79],"turning":[80],"sleeping":[87],"functional":[88],"units.":[89],"Experimental":[90],"results":[91],"show":[92],"our":[94],"achieves":[96],"50%":[97],"energy-saving":[98],"compared":[99],"with":[100],"conventional":[101],"algorithms.":[102]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}