{"id":"https://openalex.org/W4403277639","doi":"https://doi.org/10.1109/vdat63601.2024.10705748","title":"Low Latency VLSI Architecture of Histogram Equalization of Images","display_name":"Low Latency VLSI Architecture of Histogram Equalization of Images","publication_year":2024,"publication_date":"2024-09-01","ids":{"openalex":"https://openalex.org/W4403277639","doi":"https://doi.org/10.1109/vdat63601.2024.10705748"},"language":"en","primary_location":{"id":"doi:10.1109/vdat63601.2024.10705748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705748","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075988212","display_name":"Mohamed Asan Basiri M","orcid":null},"institutions":[{"id":"https://openalex.org/I61631359","display_name":"Kurnool Medical College","ror":"https://ror.org/02j3bag68","country_code":"IN","type":"education","lineage":["https://openalex.org/I170558118","https://openalex.org/I61631359"]},{"id":"https://openalex.org/I39244652","display_name":"Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram","ror":"https://ror.org/023c9pb11","country_code":"IN","type":"education","lineage":["https://openalex.org/I39244652"]},{"id":"https://openalex.org/I207223250","display_name":"Indian Institute of Information Technology Design and Manufacturing Jabalpur","ror":"https://ror.org/00gmd7q80","country_code":"IN","type":"education","lineage":["https://openalex.org/I207223250"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mohamed Asan Basiri M","raw_affiliation_strings":["IIITDM,Department of Electronics and Communication Engineering,Kurnool,India,518007"],"affiliations":[{"raw_affiliation_string":"IIITDM,Department of Electronics and Communication Engineering,Kurnool,India,518007","institution_ids":["https://openalex.org/I61631359","https://openalex.org/I207223250","https://openalex.org/I39244652"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5075988212"],"corresponding_institution_ids":["https://openalex.org/I207223250","https://openalex.org/I39244652","https://openalex.org/I61631359"],"apc_list":null,"apc_paid":null,"fwci":0.4828,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.64960092,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9908999800682068,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10627","display_name":"Advanced Image and Video Retrieval Techniques","score":0.9822999835014343,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10688","display_name":"Image and Signal Denoising Methods","score":0.9807000160217285,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.781562864780426},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7253696322441101},{"id":"https://openalex.org/keywords/histogram-equalization","display_name":"Histogram equalization","score":0.6695590019226074},{"id":"https://openalex.org/keywords/histogram","display_name":"Histogram","score":0.6416802406311035},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5428128838539124},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.44566336274147034},{"id":"https://openalex.org/keywords/adaptive-histogram-equalization","display_name":"Adaptive histogram equalization","score":0.4407983422279358},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3862684369087219},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35430479049682617},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2163204848766327},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.2012418806552887},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09369361400604248}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.781562864780426},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7253696322441101},{"id":"https://openalex.org/C136943445","wikidata":"https://www.wikidata.org/wiki/Q1970240","display_name":"Histogram equalization","level":4,"score":0.6695590019226074},{"id":"https://openalex.org/C53533937","wikidata":"https://www.wikidata.org/wiki/Q185020","display_name":"Histogram","level":3,"score":0.6416802406311035},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5428128838539124},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.44566336274147034},{"id":"https://openalex.org/C30387639","wikidata":"https://www.wikidata.org/wiki/Q4680744","display_name":"Adaptive histogram equalization","level":5,"score":0.4407983422279358},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3862684369087219},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35430479049682617},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2163204848766327},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.2012418806552887},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09369361400604248},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat63601.2024.10705748","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705748","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1628151656","https://openalex.org/W1979038119","https://openalex.org/W1995247496","https://openalex.org/W2019232927","https://openalex.org/W2025016822","https://openalex.org/W2039551633","https://openalex.org/W2124531694","https://openalex.org/W2511250243","https://openalex.org/W2511611370","https://openalex.org/W2525900780","https://openalex.org/W2917260512","https://openalex.org/W3046022610","https://openalex.org/W3195721577","https://openalex.org/W4214921324","https://openalex.org/W4226136345"],"related_works":["https://openalex.org/W2057981026","https://openalex.org/W2256021896","https://openalex.org/W2122866860","https://openalex.org/W2165297163","https://openalex.org/W2134986978","https://openalex.org/W2398368608","https://openalex.org/W1583737874","https://openalex.org/W1994424557","https://openalex.org/W2024449420","https://openalex.org/W3084145657"],"abstract_inverted_index":{"Histogram":[0],"is":[1,45],"an":[2,17],"important":[3],"feature":[4],"of":[5,21,26,32,58,88,113,122],"the":[6,27,30,43,56,63,74,78,84,89,93,111,119,126,136],"digital":[7],"images":[8,28],"used":[9],"in":[10,68,133,141],"many":[11],"image":[12],"transformations.":[13],"This":[14],"paper":[15],"proposes":[16],"efficient":[18],"VLSI":[19],"architecture":[20,121],"histogram":[22,59,75,123],"generation":[23],"and":[24,95,130,143],"equalization":[25,124],"with":[29,49,77,100],"range":[31],"pixel":[33],"values":[34],"from":[35],"0":[36],"to":[37,72,135],"255.":[38],"In":[39],"our":[40,69],"proposed":[41,70,90,96,120],"design,":[42],"delay":[44,87,127],"reduced":[46],"as":[47,139],"compared":[48],"various":[50],"existing":[51,94],"designs.":[52],"We":[53],"have":[54],"eliminated":[55],"requirement":[57],"storage":[60],"unit.":[61,81],"However,":[62],"temporal":[64],"buffers":[65],"are":[66,98],"introduced":[67],"designs":[71,138],"store":[73],"along":[76],"pipelined":[79],"divider":[80],"It":[82],"lowers":[83,125],"critical":[85],"path":[86],"design.":[91],"All":[92],"architectures":[97],"implemented":[99],"45":[101],"nm":[102],"CMOS":[103],"technology.":[104],"The":[105],"synthesis":[106],"results":[107],"reveal":[108],"that,":[109],"for":[110],"implementation":[112],"(22":[114],"\u00d7":[115],"23)-point":[116],"grey":[117],"image,":[118],"by":[128],"83%":[129],"85%,":[131],"respectively,":[132],"comparison":[134],"current":[137],"shown":[140],"[13]":[142],"[14].":[144]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-04-18T07:56:08.524223","created_date":"2025-10-10T00:00:00"}