{"id":"https://openalex.org/W4403278197","doi":"https://doi.org/10.1109/vdat63601.2024.10705742","title":"A Shift-left Approach in Qualification of Digital IPs for SoCs by Applying Advanced Automation and Data Analytics","display_name":"A Shift-left Approach in Qualification of Digital IPs for SoCs by Applying Advanced Automation and Data Analytics","publication_year":2024,"publication_date":"2024-09-01","ids":{"openalex":"https://openalex.org/W4403278197","doi":"https://doi.org/10.1109/vdat63601.2024.10705742"},"language":"en","primary_location":{"id":"doi:10.1109/vdat63601.2024.10705742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109798560","display_name":"Hirak Jyoti Chakraborty","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Hirak Jyoti Chakraborty","raw_affiliation_strings":["Infineon Technologies,Bangalore,India"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies,Bangalore,India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075276819","display_name":"Deep Ketankumar Acharya","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Deep Ketankumar Acharya","raw_affiliation_strings":["Infineon Technologies,Bangalore,India"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies,Bangalore,India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5109798560"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9752,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.75741341,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9887999892234802,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.7642220258712769},{"id":"https://openalex.org/keywords/analytics","display_name":"Analytics","score":0.6851112246513367},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5682300329208374},{"id":"https://openalex.org/keywords/data-analysis","display_name":"Data analysis","score":0.5279309749603271},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4811488389968872},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4340208172798157},{"id":"https://openalex.org/keywords/data-science","display_name":"Data science","score":0.31094199419021606},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28263625502586365},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.12260401248931885}],"concepts":[{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.7642220258712769},{"id":"https://openalex.org/C79158427","wikidata":"https://www.wikidata.org/wiki/Q485396","display_name":"Analytics","level":2,"score":0.6851112246513367},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5682300329208374},{"id":"https://openalex.org/C175801342","wikidata":"https://www.wikidata.org/wiki/Q1988917","display_name":"Data analysis","level":2,"score":0.5279309749603271},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4811488389968872},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4340208172798157},{"id":"https://openalex.org/C2522767166","wikidata":"https://www.wikidata.org/wiki/Q2374463","display_name":"Data science","level":1,"score":0.31094199419021606},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28263625502586365},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.12260401248931885},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat63601.2024.10705742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2805342204","https://openalex.org/W4378901625","https://openalex.org/W4389166648","https://openalex.org/W4389777198","https://openalex.org/W4400031992"],"related_works":["https://openalex.org/W4226266853","https://openalex.org/W4210252074","https://openalex.org/W3092201768","https://openalex.org/W2796632413","https://openalex.org/W2740083192","https://openalex.org/W2794907032","https://openalex.org/W4255802207","https://openalex.org/W4299701476","https://openalex.org/W2904574413","https://openalex.org/W3214257365"],"abstract_inverted_index":{"In":[0,35],"SoC":[1],"product":[2,38],"development":[3,39],"process,":[4],"Digital":[5,79],"IP":[6,80],"signoff":[7,19,81],"is":[8],"an":[9,36],"important":[10],"step.":[11],"Also":[12],"sometimes":[13],"time":[14],"consuming.":[15],"Some":[16],"of":[17,44,101],"the":[18,54,78,99,102],"guidelines":[20],"are:":[21],"(a)Perform":[22],"logical":[23],"synthesis":[24],"(b)Perform":[25],"Linting":[26],"(c)":[27],"Low":[28],"power":[29],"Analysis":[30],"(d)ATPG":[31],"goal":[32],"check":[33],"etc.":[34],"industrial":[37],"environment,":[40],"there":[41],"are":[42],"lot":[43],"products":[45],"(SoC)":[46],"get":[47],"developed":[48],"concurrently":[49],"in":[50,59],"tight":[51],"schedule.":[52],"Also,":[53],"future":[55],"roadmap":[56],"shows":[57],"surge":[58],"demand":[60],"for":[61],"SoC(s).":[62],"We":[63],"needed":[64],"to":[65,82,91,97],"develop":[66],"a":[67,87],"scalable,":[68],"modern,":[69],"data":[70],"driven":[71],"automation":[72],"which":[73],"not":[74],"only":[75],"should":[76],"expedite":[77],"Sub-System/SoC":[83],"but":[84],"also":[85],"creates":[86],"standardized":[88],"pluggable":[89],"interface":[90],"apply":[92],"different":[93],"shift-left":[94],"methodologies":[95],"easily":[96],"improve":[98],"quality":[100],"integration.":[103]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-04-02T15:55:50.835912","created_date":"2025-10-10T00:00:00"}