{"id":"https://openalex.org/W4403276962","doi":"https://doi.org/10.1109/vdat63601.2024.10705671","title":"Optimized Test Pattern Generation for Digital Circuits using SAT-Based ATPG and Scan Insertion Method","display_name":"Optimized Test Pattern Generation for Digital Circuits using SAT-Based ATPG and Scan Insertion Method","publication_year":2024,"publication_date":"2024-09-01","ids":{"openalex":"https://openalex.org/W4403276962","doi":"https://doi.org/10.1109/vdat63601.2024.10705671"},"language":"en","primary_location":{"id":"doi:10.1109/vdat63601.2024.10705671","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108183850","display_name":"Sandra Sugathan","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Sandra Sugathan","raw_affiliation_strings":["College of Engineering,Department of Electronics and Communication Engineering,Trivandrum,Kerala,India"],"affiliations":[{"raw_affiliation_string":"College of Engineering,Department of Electronics and Communication Engineering,Trivandrum,Kerala,India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064708617","display_name":"V R Adersh","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Adersh V R","raw_affiliation_strings":["College of Engineering,Department of Electronics and Communication Engineering,Trivandrum,Kerala,India"],"affiliations":[{"raw_affiliation_string":"College of Engineering,Department of Electronics and Communication Engineering,Trivandrum,Kerala,India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5108183850"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9923,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.76013007,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9864000082015991,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.9290322065353394},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6064096689224243},{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.527194082736969},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4490174651145935},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.42637595534324646},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.41787591576576233},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.39246666431427},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38147562742233276},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3575682044029236},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3239719569683075},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2713735103607178},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16341033577919006},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1093321442604065}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.9290322065353394},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6064096689224243},{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.527194082736969},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4490174651145935},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.42637595534324646},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.41787591576576233},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.39246666431427},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38147562742233276},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3575682044029236},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3239719569683075},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2713735103607178},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16341033577919006},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1093321442604065},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat63601.2024.10705671","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat63601.2024.10705671","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5400000214576721,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2118289054","https://openalex.org/W2118910735","https://openalex.org/W2323083271","https://openalex.org/W2616892825","https://openalex.org/W2901274320","https://openalex.org/W2902552013","https://openalex.org/W3036395324","https://openalex.org/W3037906668","https://openalex.org/W3214395308","https://openalex.org/W4212839743","https://openalex.org/W4231816245","https://openalex.org/W4319302805","https://openalex.org/W6912487589"],"related_works":["https://openalex.org/W2789883751","https://openalex.org/W2147986372","https://openalex.org/W1979305473","https://openalex.org/W2274367941","https://openalex.org/W2075356617","https://openalex.org/W2074302528","https://openalex.org/W2092894550","https://openalex.org/W2019719714","https://openalex.org/W2143881398","https://openalex.org/W2160753176"],"abstract_inverted_index":{"Testing":[0],"is":[1,19],"pivotal":[2],"in":[3,32,97,102,116,190,212],"ensuring":[4],"the":[5,25,53,59,64,82,107,123,136,152,168,177],"reliability":[6],"and":[7,34,46,93,148],"functionality":[8],"of":[9,55,61,109,138,170,179],"digital":[10,29,140],"circuit.":[11,26],"Generating":[12],"specific":[13],"test":[14,17,104,153,173,200],"inputs":[15,38],"or":[16],"vectors":[18],"essential":[20],"for":[21,163,220],"fault":[22],"detection":[23],"within":[24],"However,":[27],"as":[28],"circuits":[30,87,141],"grow":[31],"complexity":[33,115,178],"size":[35],"generating":[36],"these":[37],"becomes":[39],"increasingly":[40],"challenging":[41],"computationally.":[42],"Test":[43,47,146,149],"data":[44],"volume":[45],"time":[48,105,214],"are":[49],"critical":[50],"parameters":[51,144],"impacting":[52],"efficiency":[54,137],"circuit":[56],"testing.":[57],"In":[58],"case":[60],"sequential":[62,86],"circuits,":[63,119,165,182],"scan":[65,75,110],"insertion":[66],"approach":[67,207],"streamlines":[68],"testing":[69,117,139],"by":[70,142],"converting":[71],"regular":[72],"flip-flops":[73,76],"into":[74],"using":[77,90,157],"various":[78,221],"EDA":[79],"tools.":[80],"Using":[81],"Scan":[83],"DFT":[84],"technique,":[85,127],"were":[88,218],"tested":[89],"Synopsys":[91],"Tetramax":[92],"Fusion":[94],"Compiler,":[95],"resulting":[96],"a":[98,183,209],"remarkable":[99],"80-95%":[100],"reduction":[101,211],"total":[103],"with":[106,192],"implementation":[108],"compression.":[111],"To":[112,175],"tackle":[113],"this":[114],"combinational":[118,164,181],"we":[120],"have":[121],"used":[122],"Boolean":[124,193],"Satisfiability":[125,194],"(SAT)":[126],"leveraging":[128],"PycoSAT":[129],"solvers.":[130],"This":[131,206],"paper":[132],"focuses":[133],"on":[134],"enhancing":[135],"optimizing":[143],"like":[145],"Time":[147],"data.":[150],"Additionally,":[151],"generation":[154],"algorithm":[155],"implemented":[156],"Python":[158],"successfully":[159],"identified":[160],"equivalent":[161],"faults":[162,217],"leading":[166],"to":[167,198],"acquisition":[169],"an":[171],"optimized":[172],"set.":[174],"address":[176],"large":[180],"preprocessing":[184],"technique":[185],"called":[186],"clause":[187],"subsumption":[188],"elimination,":[189],"conjunction":[191],"(SAT),":[195],"was":[196],"utilized":[197],"generate":[199],"sets":[201],"from":[202],"extensive":[203],"DIMACS":[204],"files.":[205],"demonstrated":[208],"significant":[210],"solving":[213],"when":[215],"multiple":[216],"injected":[219],"circuits.":[222]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}