{"id":"https://openalex.org/W3213105491","doi":"https://doi.org/10.1109/vdat53777.2021.9600972","title":"Analysis of Standard Cells performance for In<sub>0.53</sub>Ga<sub>0.47</sub>As FinFET with underlap fin length for High Speed Applications","display_name":"Analysis of Standard Cells performance for In<sub>0.53</sub>Ga<sub>0.47</sub>As FinFET with underlap fin length for High Speed Applications","publication_year":2021,"publication_date":"2021-09-16","ids":{"openalex":"https://openalex.org/W3213105491","doi":"https://doi.org/10.1109/vdat53777.2021.9600972","mag":"3213105491"},"language":"en","primary_location":{"id":"doi:10.1109/vdat53777.2021.9600972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat53777.2021.9600972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055150226","display_name":"Jay Pathak","orcid":"https://orcid.org/0000-0003-2387-6809"},"institutions":[{"id":"https://openalex.org/I42014448","display_name":"Sardar Vallabhbhai National Institute of Technology Surat","ror":"https://ror.org/02y394t43","country_code":"IN","type":"education","lineage":["https://openalex.org/I42014448"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Jay Pathak","raw_affiliation_strings":["S.V. National Institute of Technology, Surat, Gujarat, India"],"affiliations":[{"raw_affiliation_string":"S.V. National Institute of Technology, Surat, Gujarat, India","institution_ids":["https://openalex.org/I42014448"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055835846","display_name":"Anand D. Darji","orcid":"https://orcid.org/0000-0003-0167-3453"},"institutions":[{"id":"https://openalex.org/I42014448","display_name":"Sardar Vallabhbhai National Institute of Technology Surat","ror":"https://ror.org/02y394t43","country_code":"IN","type":"education","lineage":["https://openalex.org/I42014448"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anand Darji","raw_affiliation_strings":["S.V. National Institute of Technology, Surat, Gujarat, India"],"affiliations":[{"raw_affiliation_string":"S.V. National Institute of Technology, Surat, Gujarat, India","institution_ids":["https://openalex.org/I42014448"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5055150226"],"corresponding_institution_ids":["https://openalex.org/I42014448"],"apc_list":null,"apc_paid":null,"fwci":0.1003,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.44803438,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41614261269569397}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41614261269569397}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat53777.2021.9600972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat53777.2021.9600972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1539094466","https://openalex.org/W1673695041","https://openalex.org/W1979042602","https://openalex.org/W1988454505","https://openalex.org/W1991676715","https://openalex.org/W2024703844","https://openalex.org/W2033756824","https://openalex.org/W2111555482","https://openalex.org/W2144970115","https://openalex.org/W2156713962","https://openalex.org/W2157367332","https://openalex.org/W2169914612","https://openalex.org/W2170162236","https://openalex.org/W2275945693","https://openalex.org/W2412028745","https://openalex.org/W2433085916","https://openalex.org/W2525146888","https://openalex.org/W2745182898","https://openalex.org/W2746249654","https://openalex.org/W2755406303","https://openalex.org/W2780983439","https://openalex.org/W2784109122","https://openalex.org/W2792807226","https://openalex.org/W2898175369","https://openalex.org/W2924775740"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2382290278","https://openalex.org/W2350741829","https://openalex.org/W2130043461","https://openalex.org/W2530322880","https://openalex.org/W1596801655"],"abstract_inverted_index":{"In":[0,14,43,93,109],"current":[1],"CMOS":[2],"technology":[3,11],"for":[4,89],"high-speed":[5],"applications":[6],"at":[7],"the":[8,85,96,129,134,138,154,168],"sub-14":[9],"nm":[10,165],"node":[12],"using":[13],"<inf":[15,19,44,48,75,105,110,114,160],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[16,20,45,49,76,106,111,115,161],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">0.53</inf>":[17,46,112],"Ga":[18,47,113],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">0.47</inf>":[21,50,116],"As":[22,51,117],"FinFETs":[23],"is":[24,53],"becoming":[25],"a":[26,57,90],"promising":[27],"choice":[28],"because":[29],"of":[30,37,98,140],"its":[31,121],"exceptional":[32],"electrical":[33],"properties.":[34],"The":[35,123],"approach":[36],"improving":[38],"FinFET":[39],"standard":[40,67,100,156],"cells":[41,101,157],"utilizing":[42],"nFinFETs":[52,118],"suggested":[54],"to":[55,83,119],"offer":[56],"platform":[58],"in":[59,108,128],"advanced":[60],"VLSI":[61],"digital":[62],"system":[63],"flow":[64],"occupying":[65],"various":[66,99],"cells.":[68],"Gate-source/drain":[69],"(G-S/D)":[70],"underlap":[71],"fin":[72],"length":[73,147],"(L":[74],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">un</inf>":[77,107,162],")":[78],"structures":[79],"are":[80],"effectively":[81],"used":[82],"reduce":[84],"short":[86],"channel":[87,146],"effects":[88],"long":[91],"time.":[92],"this":[94],"work,":[95],"implementation":[97],"with":[102,158],"different":[103,155],"L":[104,159],"understand":[120],"significance.":[122],"device":[124],"reliability":[125],"was":[126],"tested":[127],"proposed":[130],"work":[131],"by":[132,171],"varying":[133],"process":[135],"variation":[136],"on":[137,153],"height":[139],"fin,":[141],"gate":[142],"oxide":[143],"thickness,":[144],"and":[145],"offset":[148],"parameter.":[149],"Simulation":[150],"results":[151],"performed":[152],"=":[163],"3":[164],"method":[166],"indicate":[167],"minimum":[169],"delay":[170],"42.26%.":[172]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}