{"id":"https://openalex.org/W3084922492","doi":"https://doi.org/10.1109/vdat50263.2020.9190585","title":"A Highly Stable and Robust 7T SRAM Cell using Memristor","display_name":"A Highly Stable and Robust 7T SRAM Cell using Memristor","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3084922492","doi":"https://doi.org/10.1109/vdat50263.2020.9190585","mag":"3084922492"},"language":"en","primary_location":{"id":"doi:10.1109/vdat50263.2020.9190585","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074953481","display_name":"Sahan Panguluru","orcid":null},"institutions":[{"id":"https://openalex.org/I4210101034","display_name":"Birla Institute of Technology and Science - Hyderabad Campus","ror":"https://ror.org/014ctt859","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210101034","https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sahan Panguluru","raw_affiliation_strings":["Birla Institute of Technology & Science, BITS-Pilani Hyderabad Campus, Hyderabad, Telangana, India"],"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology & Science, BITS-Pilani Hyderabad Campus, Hyderabad, Telangana, India","institution_ids":["https://openalex.org/I4210101034"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011088447","display_name":"Jai Gopal Pandey","orcid":"https://orcid.org/0000-0001-9937-7438"},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jai Gopal Pandey","raw_affiliation_strings":["Integrated Systems Laboratory, CSIR - Central Electronics Engineering Research Institute, Pilani, Rajasthan"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, CSIR - Central Electronics Engineering Research Institute, Pilani, Rajasthan","institution_ids":["https://openalex.org/I41763900"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074953481"],"corresponding_institution_ids":["https://openalex.org/I4210101034"],"apc_list":null,"apc_paid":null,"fwci":0.7192,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.70543809,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.8943969011306763},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6359281539916992},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4785531163215637},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.46471866965293884},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3531077206134796},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1507205069065094},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.11552372574806213}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.8943969011306763},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6359281539916992},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4785531163215637},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.46471866965293884},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3531077206134796},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1507205069065094},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.11552372574806213}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat50263.2020.9190585","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2073818373","https://openalex.org/W2112181056","https://openalex.org/W2114853176","https://openalex.org/W2139681777","https://openalex.org/W2162651880","https://openalex.org/W2603064927","https://openalex.org/W2752340955","https://openalex.org/W2760669496","https://openalex.org/W2896543104","https://openalex.org/W2968749320","https://openalex.org/W3142526730","https://openalex.org/W4243164749","https://openalex.org/W4285719527","https://openalex.org/W6680708075","https://openalex.org/W6736339276","https://openalex.org/W6767036050"],"related_works":["https://openalex.org/W2915176329","https://openalex.org/W2969498307","https://openalex.org/W3010362863","https://openalex.org/W1494152240","https://openalex.org/W3010494226","https://openalex.org/W2539842216","https://openalex.org/W2026429700","https://openalex.org/W2510527609","https://openalex.org/W3084922492","https://openalex.org/W2396605725"],"abstract_inverted_index":{"The":[0,102,124],"ever-growing":[1],"needs":[2],"for":[3,47],"processing":[4],"on":[5],"system-on-chip":[6],"(SoC)":[7],"demands":[8],"us":[9],"to":[10,71],"scale":[11],"down":[12],"the":[13,30,58,78,94,116],"Static":[14,103],"RAM":[15],"(SRAM)":[16],"cell":[17,37,64,129],"which":[18],"occupies":[19],"around":[20],"65-75%":[21],"area":[22,49,140],"of":[23,35,115,127,141],"SoCs.":[24],"Continued":[25],"scaling":[26],"procedure":[27],"have":[28],"decreased":[29],"read":[31,125],"and":[32,92,132],"write":[33,133],"stability":[34],"SRAMs":[36],"with":[38,137],"increased":[39],"delay.":[40],"Emerging":[41],"technologies":[42],"like":[43],"Memristor":[44],"is":[45,69,85,130,135],"used":[46,84],"smaller":[48],"consumption":[50],"than":[51],"a":[52],"standard":[53],"CMOS":[54],"design":[55],"without":[56],"compromising":[57],"device's":[59],"functionality.":[60],"A":[61],"seven":[62],"transistor(7T)":[63],"at":[65],"7nm":[66,81],"feature":[67],"size":[68],"proposed":[70,79,117],"accomplish":[72],"improvements":[73],"in":[74,98],"noise":[75],"margins.":[76],"In":[77],"architecture":[80,118],"model":[82],"card":[83],"taken":[86],"from":[87],"Predictive":[88],"Technology":[89],"Model":[90],"(PTM)":[91],"all":[93],"simulations":[95],"are":[96,119],"done":[97],"Cadence":[99],"Virtuoso":[100],"tool.":[101],"Noise":[104,108,112],"Margin":[105,109,113],"(SNM),":[106],"Read":[107],"(RNM),":[110],"Write":[111],"(WNM)":[114],"210mv,":[120,121],"145mv":[122],"respectively.":[123],"time":[126,134],"1-bit":[128],"5ps":[131],"17.6ps":[136],"an":[138],"estimated":[139],"0.0291\u03bcm":[142],"<sup":[143],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[144],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[145],".":[146]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}