{"id":"https://openalex.org/W3086397373","doi":"https://doi.org/10.1109/vdat50263.2020.9190559","title":"Classification based scheduling in Heterogeneous ISA Architectures","display_name":"Classification based scheduling in Heterogeneous ISA Architectures","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3086397373","doi":"https://doi.org/10.1109/vdat50263.2020.9190559","mag":"3086397373"},"language":"en","primary_location":{"id":"doi:10.1109/vdat50263.2020.9190559","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190559","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064947330","display_name":"Nirmal Kumar Boran","orcid":"https://orcid.org/0000-0003-3942-7899"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Nirmal Kumar Boran","raw_affiliation_strings":["Computer Architecture and Dependable System Lab, Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable System Lab, Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100650824","display_name":"Dinesh Kumar Yadav","orcid":"https://orcid.org/0009-0002-4337-1111"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dinesh Kumar Yadav","raw_affiliation_strings":["Computer Architecture and Dependable System Lab, Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable System Lab, Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000529247","display_name":"Rishabh Iyer","orcid":"https://orcid.org/0000-0001-9851-463X"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rishabh Iyer","raw_affiliation_strings":["Computer Architecture and Dependable System Lab, Indian Institute of Technology Bombay, India"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Dependable System Lab, Indian Institute of Technology Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064947330"],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.4621,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.59828688,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8444575071334839},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.7040194272994995},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6605338454246521},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.6525815725326538},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.652350664138794},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6317480802536011},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5872599482536316},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.579151451587677},{"id":"https://openalex.org/keywords/a-priori-and-a-posteriori","display_name":"A priori and a posteriori","score":0.5193634629249573},{"id":"https://openalex.org/keywords/affine-transformation","display_name":"Affine transformation","score":0.4984548091888428},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.48952969908714294},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.4848986268043518},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.4657942056655884},{"id":"https://openalex.org/keywords/single-core","display_name":"Single-core","score":0.4408310055732727},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4137257933616638},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.38687020540237427},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12613660097122192}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8444575071334839},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.7040194272994995},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6605338454246521},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6525815725326538},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.652350664138794},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6317480802536011},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5872599482536316},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.579151451587677},{"id":"https://openalex.org/C75553542","wikidata":"https://www.wikidata.org/wiki/Q178161","display_name":"A priori and a posteriori","level":2,"score":0.5193634629249573},{"id":"https://openalex.org/C92757383","wikidata":"https://www.wikidata.org/wiki/Q382497","display_name":"Affine transformation","level":2,"score":0.4984548091888428},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.48952969908714294},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.4848986268043518},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.4657942056655884},{"id":"https://openalex.org/C2780365336","wikidata":"https://www.wikidata.org/wiki/Q25047934","display_name":"Single-core","level":2,"score":0.4408310055732727},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4137257933616638},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.38687020540237427},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12613660097122192},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat50263.2020.9190559","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190559","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.4699999988079071,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1656664476","https://openalex.org/W1976773142","https://openalex.org/W2013281054","https://openalex.org/W2036853599","https://openalex.org/W2066789793","https://openalex.org/W2121788702","https://openalex.org/W2125754912","https://openalex.org/W2127637835","https://openalex.org/W2138783391","https://openalex.org/W2147657366","https://openalex.org/W2150007533","https://openalex.org/W2167556016","https://openalex.org/W2170382128","https://openalex.org/W2239947352","https://openalex.org/W2569126118","https://openalex.org/W2968892132","https://openalex.org/W4237877708","https://openalex.org/W4244536239","https://openalex.org/W4251038806","https://openalex.org/W6636964530","https://openalex.org/W6649964633","https://openalex.org/W6766817600"],"related_works":["https://openalex.org/W4250432526","https://openalex.org/W2101536355","https://openalex.org/W2171175484","https://openalex.org/W2085872434","https://openalex.org/W2883183116","https://openalex.org/W2026084820","https://openalex.org/W2562747857","https://openalex.org/W2276000909","https://openalex.org/W1547865754","https://openalex.org/W3086397373"],"abstract_inverted_index":{"Heterogeneous-ISA":[0],"multi-core":[1],"architectures":[2,7,16],"are":[3],"emerging":[4],"as":[5],"promising":[6],"to":[8,32,58,74,105,132],"enhance":[9],"single-threaded":[10],"performance.":[11],"Multiple":[12],"cores":[13],"in":[14,18],"such":[15],"differ":[17],"their":[19],"Instruction":[20],"Set":[21],"Architectures":[22],"(ISAs).":[23],"To":[24],"achieve":[25],"maximum":[26],"performance":[27,103,125],"gain,":[28],"the":[29,49,76,79,82,108],"program":[30,80],"needs":[31],"be":[33,59],"divided":[34],"into":[35,81],"several":[36,100],"phases":[37],"and":[38,90],"each":[39,54,113],"phase":[40,55,77],"should":[41],"run":[42],"on":[43],"its":[44],"best":[45,50],"affine":[46,110],"core.":[47],"Hence,":[48],"affined":[51],"core":[52,85,111],"for":[53,112],"is":[56,93],"needed":[57],"known":[60],"dynamically":[61],"apriori.":[62],"In":[63],"this":[64],"work,":[65],"we":[66],"propose":[67],"a":[68,133],"classification":[69,119],"based":[70,120],"technique":[71,98],"that":[72,117],"attempts":[73],"classify":[75],"of":[78,84,88,128],"class":[83],"(in":[86],"terms":[87],"microarchitecture":[89],"ISA)":[91],"it":[92],"most":[94,109],"suited":[95],"to.":[96],"This":[97],"leverages":[99],"online":[101],"hardware":[102],"counters":[104],"accurately":[106],"predict":[107],"phase.":[114],"Results":[115],"show":[116],"our":[118],"predictor":[121],"achieves":[122],"single":[123,135],"thread":[124],"average":[126],"speedup":[127],"35.7%":[129],"with":[130],"respect":[131],"baseline":[134],"ISA":[136],"heterogeneous":[137],"architecture.":[138]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}