{"id":"https://openalex.org/W3084645253","doi":"https://doi.org/10.1109/vdat50263.2020.9190315","title":"Artificial Neural Network Model for Design Optimization of 2-stage Op-amp","display_name":"Artificial Neural Network Model for Design Optimization of 2-stage Op-amp","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3084645253","doi":"https://doi.org/10.1109/vdat50263.2020.9190315","mag":"3084645253"},"language":"en","primary_location":{"id":"doi:10.1109/vdat50263.2020.9190315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097129503","display_name":"Harsha M.V.","orcid":null},"institutions":[{"id":"https://openalex.org/I53465836","display_name":"Bangalore University","ror":"https://ror.org/050j2vm64","country_code":"IN","type":"education","lineage":["https://openalex.org/I53465836"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Harsha M.V.","raw_affiliation_strings":["Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bengaluru, India","institution_ids":["https://openalex.org/I53465836"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108401813","display_name":"B. P. Harish","orcid":null},"institutions":[{"id":"https://openalex.org/I53465836","display_name":"Bangalore University","ror":"https://ror.org/050j2vm64","country_code":"IN","type":"education","lineage":["https://openalex.org/I53465836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B. P. Harish","raw_affiliation_strings":["Department of Electrical Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University Visvesvaraya College of Engineering, Bangalore University, Bengaluru, India","institution_ids":["https://openalex.org/I53465836"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5097129503"],"corresponding_institution_ids":["https://openalex.org/I53465836"],"apc_list":null,"apc_paid":null,"fwci":0.411,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.61393256,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7219117283821106},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6525015830993652},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.6294563412666321},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.5575380921363831},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5571244359016418},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5419110059738159},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5392516851425171},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.447209894657135},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.42132604122161865},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4157668352127075},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3770853877067566},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3767108917236328},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3423812985420227},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.3237552046775818},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20583009719848633},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1749725043773651}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7219117283821106},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6525015830993652},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.6294563412666321},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.5575380921363831},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5571244359016418},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5419110059738159},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5392516851425171},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.447209894657135},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.42132604122161865},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4157668352127075},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3770853877067566},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3767108917236328},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3423812985420227},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.3237552046775818},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20583009719848633},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1749725043773651},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat50263.2020.9190315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1524759419","https://openalex.org/W1536945048","https://openalex.org/W1580635744","https://openalex.org/W1604185664","https://openalex.org/W1973505720","https://openalex.org/W2023878889","https://openalex.org/W2028166238","https://openalex.org/W2095157116","https://openalex.org/W2101377736","https://openalex.org/W2165666706","https://openalex.org/W2170444246","https://openalex.org/W2346640828","https://openalex.org/W2470990218","https://openalex.org/W2505156150","https://openalex.org/W2604319603","https://openalex.org/W2789666724","https://openalex.org/W2885447634","https://openalex.org/W2886810525","https://openalex.org/W6643700722","https://openalex.org/W6749040445"],"related_works":["https://openalex.org/W4327500672","https://openalex.org/W2545603903","https://openalex.org/W2734663060","https://openalex.org/W2066877376","https://openalex.org/W2306682566","https://openalex.org/W4318224782","https://openalex.org/W2122222688","https://openalex.org/W1933057227","https://openalex.org/W4313341368","https://openalex.org/W2945462300"],"abstract_inverted_index":{"The":[0,118],"existence":[1],"of":[2,14,24,53,69,87,93,108,137,173],"multi-dimensional":[3],"tradeoffs":[4],"among":[5],"performance":[6,131,138],"metrics":[7],"is":[8,116,121,151],"an":[9,90],"impediment":[10],"to":[11,38,66,80,103,161],"the":[12,22,39,51,106,111,124,140,158],"development":[13,52],"reliable":[15],"Electronic":[16],"Design":[17],"Automation":[18],"(EDA)":[19],"tools":[20],"for":[21,50,63,76,169],"design":[23,163,174],"analog":[25,64,88],"circuits.":[26],"To":[27],"overcome":[28],"this":[29],"limitation,":[30],"soft":[31],"computing":[32],"techniques":[33],"that":[34,153],"have":[35],"functionality":[36],"similar":[37],"human":[40],"brain":[41],"are":[42,145],"being":[43],"explored.":[44],"This":[45],"work":[46],"proposes":[47],"a":[48,54,73,94,134,166,170],"methodology":[49],"fast":[55],"and":[56,83,113,127],"accurate":[57],"Artificial":[58],"Neural":[59],"Network":[60],"(ANN)":[61],"model":[62,120,142],"circuits,":[65,89],"achieve":[67,162],"optimization":[68],"its":[70,99],"design,":[71],"considering":[72],"2-stage":[74],"op-amp":[75],"illustration.":[77],"In":[78],"order":[79],"map":[81],"complex":[82],"multiple":[84],"input-output":[85],"relationships":[86],"ANN":[91,119,141,155],"architecture":[92],"single":[95,167],"hidden":[96],"layer":[97],"with":[98],"neuron":[100],"count":[101],"selected":[102],"be":[104],"between":[105],"number":[107],"neurons":[109],"in":[110,123,165],"input":[112],"output":[114],"layers":[115],"proposed.":[117],"developed":[122],"MATLAB":[125],"environment,":[126],"trained":[128,154],"using":[129],"SPICE-generated":[130],"dataset.":[132],"For":[133],"given":[135],"set":[136,172],"metrics,":[139],"generated":[143],"designs":[144],"validated":[146],"against":[147],"SPICE":[148],"simulations.":[149],"It":[150],"demonstrated":[152],"models":[156],"substitute":[157],"circuit":[159],"simulator,":[160],"optimization,":[164],"iteration,":[168],"new":[171],"specifications.":[175]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1}],"updated_date":"2026-02-27T16:54:17.756197","created_date":"2025-10-10T00:00:00"}
