{"id":"https://openalex.org/W3086078226","doi":"https://doi.org/10.1109/vdat50263.2020.9190260","title":"A Decimal Multiplier With Improved Speed Using Semi-Parallel Iterative Approach","display_name":"A Decimal Multiplier With Improved Speed Using Semi-Parallel Iterative Approach","publication_year":2020,"publication_date":"2020-07-01","ids":{"openalex":"https://openalex.org/W3086078226","doi":"https://doi.org/10.1109/vdat50263.2020.9190260","mag":"3086078226"},"language":"en","primary_location":{"id":"doi:10.1109/vdat50263.2020.9190260","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190260","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071532575","display_name":"M.N. Spoorthi","orcid":null},"institutions":[{"id":"https://openalex.org/I181514455","display_name":"International Institute of Information Technology Bangalore","ror":"https://ror.org/05h9eqy10","country_code":"IN","type":"education","lineage":["https://openalex.org/I181514455"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"M.N. Spoorthi","raw_affiliation_strings":["CEEMS Lab, International Institute of Information Technology Bangalore, Bengaluru, India"],"raw_orcid":"https://orcid.org/0000-0001-5277-126X","affiliations":[{"raw_affiliation_string":"CEEMS Lab, International Institute of Information Technology Bangalore, Bengaluru, India","institution_ids":["https://openalex.org/I181514455"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020532266","display_name":"Subir Kumar Roy","orcid":"https://orcid.org/0000-0002-3554-1312"},"institutions":[{"id":"https://openalex.org/I181514455","display_name":"International Institute of Information Technology Bangalore","ror":"https://ror.org/05h9eqy10","country_code":"IN","type":"education","lineage":["https://openalex.org/I181514455"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Subir K. Roy","raw_affiliation_strings":["VLSI Systems, International Institute of Information Technology Bangalore, Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Systems, International Institute of Information Technology Bangalore, Bengaluru, India","institution_ids":["https://openalex.org/I181514455"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5071532575"],"corresponding_institution_ids":["https://openalex.org/I181514455"],"apc_list":null,"apc_paid":null,"fwci":0.289,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63584084,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/decimal","display_name":"Decimal","score":0.8368611335754395},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7069790959358215},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6875439286231995},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5994823575019836},{"id":"https://openalex.org/keywords/iterative-method","display_name":"Iterative method","score":0.5496599674224854},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5418996810913086},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4863198697566986},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.47013431787490845},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.44058820605278015},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.35006004571914673},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3309605121612549}],"concepts":[{"id":"https://openalex.org/C65045869","wikidata":"https://www.wikidata.org/wiki/Q81365","display_name":"Decimal","level":2,"score":0.8368611335754395},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7069790959358215},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6875439286231995},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5994823575019836},{"id":"https://openalex.org/C159694833","wikidata":"https://www.wikidata.org/wiki/Q2321565","display_name":"Iterative method","level":2,"score":0.5496599674224854},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5418996810913086},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4863198697566986},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.47013431787490845},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.44058820605278015},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.35006004571914673},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3309605121612549},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vdat50263.2020.9190260","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vdat50263.2020.9190260","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 24th International Symposium on VLSI Design and Test (VDAT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1578007657","https://openalex.org/W1584008964","https://openalex.org/W1584707396","https://openalex.org/W1587217691","https://openalex.org/W2014396665","https://openalex.org/W2021017629","https://openalex.org/W2043066816","https://openalex.org/W2047039687","https://openalex.org/W2051488784","https://openalex.org/W2065336757","https://openalex.org/W2074746869","https://openalex.org/W2094544799","https://openalex.org/W2106191211","https://openalex.org/W2110538940","https://openalex.org/W2112537667","https://openalex.org/W2121202037","https://openalex.org/W2133140834","https://openalex.org/W2142454275","https://openalex.org/W2146871557","https://openalex.org/W2154763551","https://openalex.org/W2162383260","https://openalex.org/W2169559417","https://openalex.org/W2170071450","https://openalex.org/W2279858806","https://openalex.org/W2547482522","https://openalex.org/W2594291537","https://openalex.org/W2803886691","https://openalex.org/W4210830821"],"related_works":["https://openalex.org/W2013839957","https://openalex.org/W2516369861","https://openalex.org/W3196607417","https://openalex.org/W177032641","https://openalex.org/W2502533382","https://openalex.org/W1967012415","https://openalex.org/W2961151343","https://openalex.org/W2468097068","https://openalex.org/W3028928340","https://openalex.org/W279796016"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,47],"semi-parallel":[4,32,72],"iterative":[5,49,73],"decimal":[6,39,82],"multiplier.":[7],"The":[8,54],"Proposed":[9],"multiplier":[10],"uses":[11],"BCD-8421":[12],"encoding":[13],"which":[14],"does":[15],"not":[16],"require":[17],"any":[18],"recoding":[19],"as":[20],"compared":[21],"to":[22],"all":[23],"the":[24,28,63,66,70],"implementations":[25],"reported":[26,93],"in":[27,94],"literature.":[29,95],"It":[30],"employs":[31],"partial":[33,43,50],"product":[34,44,51],"generation":[35],"for":[36,42],"faster":[37],"multiplication,":[38],"4:2":[40],"adder":[41],"reduction":[45,52],"and":[46,59,84],"novel":[48],"approach.":[53],"proposed":[55,71],"design":[56,74],"is":[57],"implemented":[58],"verified":[60],"using":[61],"FPGA,":[62],"results":[64],"of":[65],"implementation":[67],"show":[68],"that":[69,90],"performs":[75],"better":[76],"with":[77,87],"lesser":[78],"delay":[79],"than":[80],"other":[81],"multipliers":[83,86],"binary":[85],"double":[88],"precision":[89],"have":[91],"been":[92]},"counts_by_year":[{"year":2023,"cited_by_count":2}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}