{"id":"https://openalex.org/W2563879098","doi":"https://doi.org/10.1109/uemcon.2016.7777857","title":"An RTL power optimization technique based on System Verilog assertions","display_name":"An RTL power optimization technique based on System Verilog assertions","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2563879098","doi":"https://doi.org/10.1109/uemcon.2016.7777857","mag":"2563879098"},"language":"en","primary_location":{"id":"doi:10.1109/uemcon.2016.7777857","is_oa":false,"landing_page_url":"https://doi.org/10.1109/uemcon.2016.7777857","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019518921","display_name":"Khaled Ben Khalifa","orcid":"https://orcid.org/0000-0001-6758-1944"},"institutions":[{"id":"https://openalex.org/I84524832","display_name":"Alexandria University","ror":"https://ror.org/00mzz1w90","country_code":"EG","type":"education","lineage":["https://openalex.org/I84524832"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Khaled Khalifa","raw_affiliation_strings":["Alexandria University, Alexandria, Egypt"],"affiliations":[{"raw_affiliation_string":"Alexandria University, Alexandria, Egypt","institution_ids":["https://openalex.org/I84524832"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028133110","display_name":"Khaled Salah","orcid":"https://orcid.org/0000-0002-2310-2558"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Khaled Salah","raw_affiliation_strings":["Mentor Graphics, Cairo, Egypt"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Cairo, Egypt","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5019518921"],"corresponding_institution_ids":["https://openalex.org/I84524832"],"apc_list":null,"apc_paid":null,"fwci":0.946,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.75277412,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9855999946594238,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9843999743461609,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8547242879867554},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7288564443588257},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.6491384506225586},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5752615928649902},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5212405323982239},{"id":"https://openalex.org/keywords/directive","display_name":"Directive","score":0.4523922801017761},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43301117420196533},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33825087547302246},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3349553942680359},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.32275277376174927},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17907392978668213},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14788609743118286},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1427331566810608}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8547242879867554},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7288564443588257},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.6491384506225586},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5752615928649902},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5212405323982239},{"id":"https://openalex.org/C2779547435","wikidata":"https://www.wikidata.org/wiki/Q1121492","display_name":"Directive","level":2,"score":0.4523922801017761},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43301117420196533},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33825087547302246},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3349553942680359},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.32275277376174927},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17907392978668213},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14788609743118286},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1427331566810608},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/uemcon.2016.7777857","is_oa":false,"landing_page_url":"https://doi.org/10.1109/uemcon.2016.7777857","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W567973435","https://openalex.org/W1493602245"],"related_works":["https://openalex.org/W3033520411","https://openalex.org/W2322198081","https://openalex.org/W4213457160","https://openalex.org/W2539947270","https://openalex.org/W1761969858","https://openalex.org/W2391854357","https://openalex.org/W4238487776","https://openalex.org/W3114194214","https://openalex.org/W2132512458","https://openalex.org/W4312121077"],"abstract_inverted_index":{"This":[0,130,188],"paper":[1,189],"presents":[2,225],"a":[3,96,211,226],"novel":[4],"technique":[5,21,40,50,57,84,94,98,108,131,155,196,207],"based":[6],"on":[7,102],"System":[8],"Verilog":[9],"assertions":[10],"to":[11,25,42,65,72,86,147,192,199,242],"optimize":[12],"the":[13,23,38,43,48,69,74,78,88,103,110,114,120,142,149,157,160,167,171,194,206,220,229,235,238,243,247],"consumed":[14,75,168,230],"power":[15,33,76,150,169,231],"of":[16,77,113,153,159,170,210,237,246],"RTL":[17,28,213,239],"designs.":[18],"The":[19,35,55,80,106],"proposed":[20,39,195],"helps":[22],"designer":[24,36],"enhance":[26,68],"his":[27,52],"code":[29,71,208,240],"towards":[30],"achieving":[31],"low":[32],"design.":[34,79],"codes":[37],"according":[41,241],"design":[44,70,90,104,172,181,201],"specifications":[45,202],"and":[46,67,135,203,224,233],"integrates":[47],"coded":[49,56,107,248],"into":[51],"test":[53],"bench.":[54],"generates":[58],"directive":[59,222,244],"massages":[60,223,245],"which":[61,124],"will":[62],"be":[63,133],"followed":[64],"modify":[66],"reduce":[73],"idea":[81],"behind":[82],"this":[83,93,154,165],"is":[85,95,173],"monitor":[87],"whole":[89],"signals.":[91],"Thus,":[92],"design-dependent":[97],"as":[99,176],"it":[100,118,177,217],"depends":[101],"specifications.":[105],"determines":[109],"targeted":[111],"signals":[112,123],"specific":[115],"input":[116],"then":[117],"displays":[119],"mistakenly":[121],"setting":[122],"may":[125],"consume":[126],"additional":[127,185],"wasted":[128,186],"power.":[129,187],"can":[132],"applied":[134],"included":[136],"in":[137],"any":[138,200],"verification":[139],"framework":[140],"like":[141],"Universal":[143],"Verification":[144],"Methodology":[145],"(UVM)":[146],"integrate":[148],"optimization":[151],"feature":[152],"with":[156,197],"features":[158],"used":[161],"framework.":[162],"Through":[163],"applying":[164],"technique,":[166],"significantly":[174],"reduced":[175],"catches":[178],"each":[179],"unused":[180],"signal":[182],"that":[183],"consumes":[184],"explains":[190],"how":[191],"apply":[193],"respect":[198],"also":[204,218],"provides":[205],"itself":[209],"simple":[212],"case":[214],"study.":[215],"Moreover,":[216],"attaches":[219],"resultant":[221],"comparison":[227],"between":[228],"before":[232],"after":[234],"modification":[236],"technique.":[249]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}