{"id":"https://openalex.org/W2565063172","doi":"https://doi.org/10.1109/uemcon.2016.7777840","title":"Arithmetic circuit design with memristor based high fan-out logic gates","display_name":"Arithmetic circuit design with memristor based high fan-out logic gates","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2565063172","doi":"https://doi.org/10.1109/uemcon.2016.7777840","mag":"2565063172"},"language":"en","primary_location":{"id":"doi:10.1109/uemcon.2016.7777840","is_oa":false,"landing_page_url":"https://doi.org/10.1109/uemcon.2016.7777840","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083001601","display_name":"Nagaraja Revanna","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nagaraja Revanna","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028439610","display_name":"Earl E. Swartzlander","orcid":"https://orcid.org/0000-0002-8699-5277"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Earl E. Swartzlander","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5083001601"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14574084,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"61","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8141337633132935},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7006144523620605},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6588174104690552},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6408847570419312},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5834249258041382},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5464382171630859},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5242804884910583},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5174915790557861},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.4675762951374054},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.45976561307907104},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.4540274441242218},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41103285551071167},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.36602523922920227},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2172340452671051},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20543858408927917},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.20475232601165771},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19199001789093018},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17804324626922607},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.1552787721157074},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0774054229259491}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8141337633132935},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7006144523620605},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6588174104690552},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6408847570419312},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5834249258041382},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5464382171630859},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5242804884910583},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5174915790557861},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.4675762951374054},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.45976561307907104},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4540274441242218},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41103285551071167},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.36602523922920227},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2172340452671051},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20543858408927917},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.20475232601165771},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19199001789093018},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17804324626922607},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.1552787721157074},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0774054229259491},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/uemcon.2016.7777840","is_oa":false,"landing_page_url":"https://doi.org/10.1109/uemcon.2016.7777840","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1578783943","https://openalex.org/W2006097283","https://openalex.org/W2025674646","https://openalex.org/W2036687738","https://openalex.org/W2052293768","https://openalex.org/W2066280488","https://openalex.org/W2075496750","https://openalex.org/W2081729575","https://openalex.org/W2093171054","https://openalex.org/W2112181056","https://openalex.org/W2162651880","https://openalex.org/W2335248059","https://openalex.org/W2542473330","https://openalex.org/W6702972942"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2017528947","https://openalex.org/W1553855433","https://openalex.org/W1593362825","https://openalex.org/W2171918386","https://openalex.org/W1529529399","https://openalex.org/W2082591327","https://openalex.org/W2155174752","https://openalex.org/W2102499515","https://openalex.org/W2786283752"],"abstract_inverted_index":{"The":[0,15,49,90,112],"application":[1],"of":[2,27,51,60,74,77,114,127],"memristors":[3,29],"in":[4,18],"logic":[5,66,78,110],"operations":[6,33,86],"have":[7],"recently":[8],"gained":[9],"importance":[10],"and":[11,36,45,121,129],"are":[12,124,131],"being":[13],"investigated.":[14],"work":[16],"presented":[17],"this":[19],"paper":[20],"describes":[21],"a":[22,115],"new":[23],"low":[24],"power":[25],"technique":[26,59],"using":[28,61,69],"to":[30,64,87,100,104,133],"perform":[31,65],"arithmetic":[32],"like":[34],"addition":[35],"multiplication.":[37],"It":[38],"focuses":[39],"on":[40],"reducing":[41],"the":[42,72,105],"hardware":[43],"costs":[44],"associated":[46],"design":[47,113],"complexity.":[48],"idea":[50],"\u201clogic":[52],"implication\u201d":[53],"is":[54],"combined":[55],"with":[56],"an":[57,94],"analog":[58],"current":[62,70],"mirrors":[63],"operations.":[67],"By":[68],"mirrors,":[71],"problem":[73],"limited":[75],"fan-out":[76],"implication":[79],"can":[80,97],"be":[81,98],"overcome,":[82],"enabling":[83],"more":[84],"parallel":[85],"run":[88],"together.":[89],"delay":[91],"for":[92],"even":[93],"XOR":[95],"operation":[96],"reduced":[99],"1":[101],"cycle,":[102],"compared":[103,132],"5":[106],"cycles":[107],"taken":[108],"by":[109],"implication.":[111],"full":[116],"adder,":[117],"ripple":[118],"carry":[119],"adder":[120],"array":[122],"multiplier":[123],"described.":[125],"Metrics":[126],"area":[128],"latency":[130],"previous":[134],"works.":[135]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}