{"id":"https://openalex.org/W7154278795","doi":"https://doi.org/10.1109/tvlsi.2026.3682042","title":"Glitch-Aware Optimization of 4-2 Compressor-Based Approximate Multipliers","display_name":"Glitch-Aware Optimization of 4-2 Compressor-Based Approximate Multipliers","publication_year":2026,"publication_date":"2026-04-14","ids":{"openalex":"https://openalex.org/W7154278795","doi":"https://doi.org/10.1109/tvlsi.2026.3682042"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2026.3682042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2026.3682042","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014796749","display_name":"T Li","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tong Li","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0003-2168-7828","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071710813","display_name":"Tongjing Wu","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tongjing Wu","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-7393-407X","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ao Liu","orcid":"https://orcid.org/0000-0001-9899-9657"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ao Liu","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0001-9899-9657","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019717600","display_name":"Honglan Jiang","orcid":"https://orcid.org/0000-0003-3705-4240"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Honglan Jiang","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0003-3705-4240","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121532572","display_name":"Jianfei Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfei Jiang","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5521-6197","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063554298","display_name":"Qin Wang","orcid":"https://orcid.org/0000-0002-6559-5207"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qin Wang","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-6559-5207","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5128871932","display_name":"Zhigang Mao","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhigang Mao","raw_affiliation_strings":["School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0001-9431-9853","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.37825507,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"6","first_page":"1800","last_page":"1813"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9172000288963318,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9172000288963318,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.023000000044703484,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.012600000016391277,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/optimization-problem","display_name":"Optimization problem","score":0.30469998717308044},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.2971999943256378},{"id":"https://openalex.org/keywords/constrained-optimization","display_name":"Constrained optimization","score":0.28130000829696655},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.27219998836517334},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.27059999108314514}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.438400000333786},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4133000075817108},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.36489999294281006},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3400000035762787},{"id":"https://openalex.org/C28826006","wikidata":"https://www.wikidata.org/wiki/Q33521","display_name":"Applied mathematics","level":1,"score":0.33329999446868896},{"id":"https://openalex.org/C137836250","wikidata":"https://www.wikidata.org/wiki/Q984063","display_name":"Optimization problem","level":2,"score":0.30469998717308044},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.2971999943256378},{"id":"https://openalex.org/C55660270","wikidata":"https://www.wikidata.org/wiki/Q5164377","display_name":"Constrained optimization","level":2,"score":0.28130000829696655},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.27219998836517334},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.27059999108314514},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.2639999985694885}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2026.3682042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2026.3682042","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.55696702003479,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Approximate":[0],"multipliers":[1,33,116],"have":[2],"widely":[3],"been":[4],"used":[5],"in":[6,27,122,202],"error-resilient":[7],"applications":[8],"with":[9,197],"hardware-efficient":[10],"and":[11,20,30,86,96,125,153],"relaxed":[12],"precision":[13],"requirements,":[14],"such":[15],"as":[16,49],"multimedia":[17],"signal":[18,54,141],"processing":[19],"deep":[21],"learning.":[22],"Aiming":[23],"to":[24,52,60,132,193,215],"achieve":[25,119,186],"improvements":[26,205],"power":[28,137],"efficiency":[29,154],"performance,":[31],"approximate":[32,66,111,149,178,195,217],"are":[34,56,162],"generally":[35],"designed":[36],"by":[37,103,164,182],"simplifying":[38],"the":[39,43,94,109,114,123,135,156,177,183,198,209],"implementation":[40],"circuits.":[41],"However,":[42],"redundant":[44],"switching":[45],"activities":[46],"(also":[47],"known":[48],"glitches)":[50],"due":[51],"unbalanced":[53],"paths":[55],"seldom":[57],"considered,":[58],"leading":[59],"significant":[61,120],"dynamic":[62,136],"power.":[63],"Moreover,":[64,208],"prior":[65],"designs":[67,158,196],"often":[68],"overlook":[69],"transistor":[70],"sizing":[71],"optimization,":[72],"which":[73,99],"limits":[74],"their":[75],"potential":[76],"for":[77,89,147,206],"power\u2013delay":[78,188],"efficiency.":[79],"This":[80],"article":[81],"proposes":[82],"a":[83,139],"custom":[84],"design":[85],"optimization":[87,211],"framework":[88,185,212],"approximately":[90],"4-2":[91,112,179,218],"compressors":[92,180],"at":[93],"structural":[95],"circuit":[97],"levels,":[98],"effectively":[100],"reduces":[101],"glitches":[102],"balancing":[104],"output":[105],"delays.":[106],"Based":[107],"on":[108,170],"devised":[110],"compressors,":[113],"constructed":[115],"can":[117],"then":[118],"reductions":[121,191],"generation":[124],"propagation":[126],"of":[127,155],"spurious":[128],"activities.":[129],"In":[130],"addition,":[131],"further":[133],"reduce":[134],"consumption,":[138],"delay-aware":[140],"routing":[142],"(DASR)":[143],"strategy":[144],"is":[145,213],"introduced":[146],"interconnecting":[148],"compressors.":[150],"The":[151,167],"stability":[152],"proposed":[157,184,210],"under":[159],"varying":[160],"conditions":[161],"verified":[163],"extensive":[165],"simulations.":[166],"experimental":[168],"results":[169],"HLMC":[171],"28-nm":[172],"CMOS":[173],"technology":[174],"show":[175],"that":[176],"obtained":[181],"10.4%\u201352.1%":[187],"product":[189],"(PDP)":[190],"compared":[192],"existing":[194],"same":[199],"accuracy,":[200],"resulting":[201],"5.20%\u201333.1%":[203],"PDP":[204],"multipliers.":[207],"generalizable":[214],"arbitrary":[216],"compressor":[219],"designs.":[220]},"counts_by_year":[],"updated_date":"2026-06-03T06:16:58.514037","created_date":"2026-04-15T00:00:00"}