{"id":"https://openalex.org/W7128434052","doi":"https://doi.org/10.1109/tvlsi.2026.3657601","title":"A Hardware Attack Secure SRAM: A HAS-16T SRAM Cell Resistant to Side Channel Attacks and Fault-Injection Attacks","display_name":"A Hardware Attack Secure SRAM: A HAS-16T SRAM Cell Resistant to Side Channel Attacks and Fault-Injection Attacks","publication_year":2026,"publication_date":"2026-02-09","ids":{"openalex":"https://openalex.org/W7128434052","doi":"https://doi.org/10.1109/tvlsi.2026.3657601"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2026.3657601","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2026.3657601","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068846182","display_name":"Priyanka Sharma","orcid":"https://orcid.org/0000-0002-9926-2697"},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Priyanka Sharma","raw_affiliation_strings":["Department of Electronics Instrumentation, Institute of Engineering and Technology, Devi Ahilya Vishwavidyalaya, Indore, Madhya Pradesh, India"],"raw_orcid":"https://orcid.org/0000-0002-9926-2697","affiliations":[{"raw_affiliation_string":"Department of Electronics Instrumentation, Institute of Engineering and Technology, Devi Ahilya Vishwavidyalaya, Indore, Madhya Pradesh, India","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5125459360","display_name":"Nitesh Kumar Soni","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119567","display_name":"Medi-Caps University","ror":"https://ror.org/02svf5f06","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210119567"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Nitesh Kumar Soni","raw_affiliation_strings":["Department of Electronics Engineering, Medicaps University, Indore, Madhya Pradesh, India"],"raw_orcid":"https://orcid.org/0000-0002-9946-0212","affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, Medicaps University, Indore, Madhya Pradesh, India","institution_ids":["https://openalex.org/I4210119567"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063975084","display_name":"Vaibhav Neema","orcid":"https://orcid.org/0000-0003-0922-373X"},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vaibhav Neema","raw_affiliation_strings":["Department of Electronics and Telecommunication, Institute of Engineering and Technology, Devi Ahilya Vishwavidyalaya, Indore, Madhya Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication, Institute of Engineering and Technology, Devi Ahilya Vishwavidyalaya, Indore, Madhya Pradesh, India","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048924732","display_name":"Shailesh Singh Chouhan","orcid":"https://orcid.org/0000-0002-6055-3198"},"institutions":[{"id":"https://openalex.org/I190632392","display_name":"Lule\u00e5 University of Technology","ror":"https://ror.org/016st3p78","country_code":"SE","type":"education","lineage":["https://openalex.org/I190632392"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Shailesh Singh Chouhan","raw_affiliation_strings":["Department of Computer Science, Electrical and Space Engineering, Lule&#x00E5; University of Technology, Lule&#x00E5;, Norbotten, Sweden"],"raw_orcid":"https://orcid.org/0000-0002-6055-3198","affiliations":[{"raw_affiliation_string":"Department of Computer Science, Electrical and Space Engineering, Lule&#x00E5; University of Technology, Lule&#x00E5;, Norbotten, Sweden","institution_ids":["https://openalex.org/I190632392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5125440500","display_name":"Rakesh Singhai","orcid":null},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rakesh Singhai","raw_affiliation_strings":["Devi Ahilya Vishwavidyalaya, Indore, Madhya Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Devi Ahilya Vishwavidyalaya, Indore, Madhya Pradesh, India","institution_ids":["https://openalex.org/I138272832"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15165828,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"4","first_page":"1331","last_page":"1342"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.942799985408783,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.942799985408783,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.023800000548362732,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.022600000724196434,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-security-module","display_name":"Hardware security module","score":0.5580000281333923},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5328999757766724},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.48339998722076416},{"id":"https://openalex.org/keywords/side-channel-attack","display_name":"Side channel attack","score":0.48240000009536743},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.4717999994754791},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.4327999949455261},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.3571000099182129},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.325300008058548}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6008999943733215},{"id":"https://openalex.org/C39217717","wikidata":"https://www.wikidata.org/wiki/Q1432354","display_name":"Hardware security module","level":3,"score":0.5580000281333923},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5328999757766724},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.48339998722076416},{"id":"https://openalex.org/C49289754","wikidata":"https://www.wikidata.org/wiki/Q2267081","display_name":"Side channel attack","level":3,"score":0.48240000009536743},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.4717999994754791},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4650999903678894},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.4327999949455261},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.3571000099182129},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.325300008058548},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.3010999858379364},{"id":"https://openalex.org/C11560541","wikidata":"https://www.wikidata.org/wiki/Q1756025","display_name":"Replay attack","level":3,"score":0.29429998993873596},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29319998621940613},{"id":"https://openalex.org/C33884865","wikidata":"https://www.wikidata.org/wiki/Q1254335","display_name":"Cryptographic protocol","level":3,"score":0.28690001368522644},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.28380000591278076},{"id":"https://openalex.org/C53533937","wikidata":"https://www.wikidata.org/wiki/Q185020","display_name":"Histogram","level":3,"score":0.2655999958515167},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.26080000400543213},{"id":"https://openalex.org/C94520183","wikidata":"https://www.wikidata.org/wiki/Q190746","display_name":"Advanced Encryption Standard","level":3,"score":0.2524999976158142},{"id":"https://openalex.org/C152763109","wikidata":"https://www.wikidata.org/wiki/Q1228841","display_name":"Modular exponentiation","level":4,"score":0.25060001015663147},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2026.3657601","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2026.3657601","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1558671776","https://openalex.org/W2071159343","https://openalex.org/W2508872104","https://openalex.org/W2606606368","https://openalex.org/W2734814518","https://openalex.org/W2806210915","https://openalex.org/W2905238865","https://openalex.org/W3142628360","https://openalex.org/W3162523375","https://openalex.org/W4285163035","https://openalex.org/W4383724621","https://openalex.org/W4386320364","https://openalex.org/W4394854716","https://openalex.org/W4396689076","https://openalex.org/W4404917295","https://openalex.org/W4406293394","https://openalex.org/W4408071464","https://openalex.org/W4410427556","https://openalex.org/W4410852590","https://openalex.org/W4411142883","https://openalex.org/W4411405932","https://openalex.org/W4413155082","https://openalex.org/W4414404789","https://openalex.org/W4414647311","https://openalex.org/W4415736121","https://openalex.org/W4417146568"],"related_works":[],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"the":[3,91,103,108,140],"HAS-16T":[4,141],"static":[5,111],"random":[6],"access":[7],"memory":[8],"(SRAM)":[9],"cell,":[10],"a":[11,84,127],"novel":[12],"16-transistor":[13],"design":[14,105],"implemented":[15],"in":[16,102],"45":[17],"nm":[18],"CMOS":[19],"technology":[20],"to":[21,48,134,160],"achieve":[22],"robust":[23],"security":[24,62,86],"against":[25],"side-channel":[26],"attacks":[27,32,56],"(SCAs)":[28],"and":[29,43,58,80,122,136,150,158],"fault":[30],"injection":[31],"(FIAs).":[33],"The":[34],"cell":[35],"integrates":[36],"sleep":[37],"transistors,":[38],"loop-cut":[39],"mechanisms,":[40],"prewrite":[41],"conditioning,":[42],"an":[44],"inverter":[45],"feedback":[46],"loop":[47],"mitigate":[49],"leakage":[50,124],"power":[51],"analysis":[52,55],"(LPA),":[53],"timing":[54],"(TAAs),":[57],"FIAs.":[59],"A":[60],"comprehensive":[61],"measure,":[63],"based":[64],"on":[65],"Monte":[66],"Carlo":[67],"simulations":[68],"(1000":[69],"samples,":[70],"1":[71],"V,$27~^{\\circ":[72],"}":[73],"$C),":[74],"quantifies":[75],"resistance":[76],"through":[77],"histogram":[78],"overlap":[79],"failure":[81],"probability,":[82],"yielding":[83],"total":[85],"matrix":[87],"(SMTotal)":[88],"of":[89],"98.68%,":[90],"highest":[92],"among":[93],"evaluated":[94],"cells":[95],"(e.g.,":[96],"6T:":[97],"38.37%,":[98],"EQ-14T:":[99],"68.91%).":[100],"Simulations":[101],"Cadence":[104],"environment":[106],"reveal":[107],"HAS-16T\u2019s":[109],"second-highest":[110,123],"noise":[112],"margin":[113],"(SNM),":[114],"moderate":[115],"read/write":[116],"delays,":[117],"second-lowest":[118],"write":[119],"dynamic":[120],"power,":[121,125],"reflecting":[126],"balanced":[128],"tradeoff":[129],"for":[130,148],"security-critical":[131],"applications.":[132],"Compared":[133],"conventional":[135],"secure":[137],"SRAM":[138],"designs,":[139],"offers":[142],"unparalleled":[143],"protection,":[144],"making":[145],"it":[146],"ideal":[147],"cryptographic":[149],"embedded":[151],"systems.":[152],"Future":[153],"work":[154],"includes":[155],"area":[156],"optimization":[157],"scalability":[159],"advanced":[161],"process":[162],"nodes.":[163]},"counts_by_year":[],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2026-02-10T00:00:00"}
