{"id":"https://openalex.org/W7127128184","doi":"https://doi.org/10.1109/tvlsi.2026.3656539","title":"RAEnc: A Stall-Less Metadata Compression Framework for Return Address Integrity on High-Performance Embedded Processors","display_name":"RAEnc: A Stall-Less Metadata Compression Framework for Return Address Integrity on High-Performance Embedded Processors","publication_year":2026,"publication_date":"2026-02-02","ids":{"openalex":"https://openalex.org/W7127128184","doi":"https://doi.org/10.1109/tvlsi.2026.3656539"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2026.3656539","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2026.3656539","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5146670326","display_name":"Kaixuan Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kaixuan Wang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073709403","display_name":"Zikang Zhou","orcid":"https://orcid.org/0009-0006-2530-3886"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zikang Zhou","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0006-2530-3886","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5123975535","display_name":"Kanheng Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kanheng Jiang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5124867848","display_name":"Yifan Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yifan Zhao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0001-7304-8206","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5124774823","display_name":"Jun Han","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Han","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5245-0754","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10275155,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"4","first_page":"1303","last_page":"1316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.002400000113993883,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.002300000051036477,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5429999828338623},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.49880000948905945},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.46799999475479126},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.4596000015735626},{"id":"https://openalex.org/keywords/timing-attack","display_name":"Timing attack","score":0.42410001158714294},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.41990000009536743},{"id":"https://openalex.org/keywords/metadata","display_name":"Metadata","score":0.4081999957561493},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.3700999915599823}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8373000025749207},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6098999977111816},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5429999828338623},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.49880000948905945},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.46799999475479126},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.4596000015735626},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.43230000138282776},{"id":"https://openalex.org/C28420585","wikidata":"https://www.wikidata.org/wiki/Q2665075","display_name":"Timing attack","level":4,"score":0.42410001158714294},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.41990000009536743},{"id":"https://openalex.org/C93518851","wikidata":"https://www.wikidata.org/wiki/Q180160","display_name":"Metadata","level":2,"score":0.4081999957561493},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.3700999915599823},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.3626999855041504},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.35420000553131104},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.35269999504089355},{"id":"https://openalex.org/C33884865","wikidata":"https://www.wikidata.org/wiki/Q1254335","display_name":"Cryptographic protocol","level":3,"score":0.32190001010894775},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31060001254081726},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.30399999022483826},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.2858999967575073},{"id":"https://openalex.org/C33762810","wikidata":"https://www.wikidata.org/wiki/Q461671","display_name":"Data integrity","level":2,"score":0.2711000144481659},{"id":"https://openalex.org/C93996380","wikidata":"https://www.wikidata.org/wiki/Q44127","display_name":"Server","level":2,"score":0.26109999418258667},{"id":"https://openalex.org/C141441539","wikidata":"https://www.wikidata.org/wiki/Q1970908","display_name":"Boom","level":2,"score":0.2558000087738037},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2515999972820282},{"id":"https://openalex.org/C180016635","wikidata":"https://www.wikidata.org/wiki/Q2712821","display_name":"Compression (physics)","level":2,"score":0.25130000710487366},{"id":"https://openalex.org/C11560541","wikidata":"https://www.wikidata.org/wiki/Q1756025","display_name":"Replay attack","level":3,"score":0.25119999051094055}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2026.3656539","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2026.3656539","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6821509003639221,"display_name":"Peace, Justice and strong institutions","id":"https://metadata.un.org/sdg/16"}],"awards":[{"id":"https://openalex.org/G2519052758","display_name":"\u81ea\u611f\u77e5\u81ea\u7ec4\u7ec7\u5f02\u6784\u4f17\u6838\u667a\u80fd\u82af\u7247\u7684\u4e92\u8fde\u4e0e\u5b58\u50a8\u6280\u672f\u7814\u7a76","funder_award_id":"61934002","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4369517068","display_name":null,"funder_award_id":"62234008","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W1925495923","https://openalex.org/W1964132576","https://openalex.org/W1969338270","https://openalex.org/W1969501726","https://openalex.org/W1983394510","https://openalex.org/W2020208333","https://openalex.org/W2033593513","https://openalex.org/W2042856445","https://openalex.org/W2072402822","https://openalex.org/W2162800072","https://openalex.org/W2346595863","https://openalex.org/W2398192538","https://openalex.org/W2753562754","https://openalex.org/W2784642434","https://openalex.org/W2899759798","https://openalex.org/W2900500071","https://openalex.org/W2901207456","https://openalex.org/W2903910116","https://openalex.org/W2914212514","https://openalex.org/W2939057911","https://openalex.org/W2945027685","https://openalex.org/W3012136925","https://openalex.org/W3033257916","https://openalex.org/W3033299617","https://openalex.org/W3042944763","https://openalex.org/W3087256628","https://openalex.org/W3091525875","https://openalex.org/W3091997824","https://openalex.org/W3159665428","https://openalex.org/W3162727592","https://openalex.org/W3190533156","https://openalex.org/W4220653854","https://openalex.org/W4251810237","https://openalex.org/W4280513790","https://openalex.org/W4281779787","https://openalex.org/W4384948684","https://openalex.org/W4392309884","https://openalex.org/W4406856630","https://openalex.org/W4407942556","https://openalex.org/W4413679921"],"related_works":[],"abstract_inverted_index":{"Protecting":[0],"return":[1,83],"address":[2,44,84],"integrity":[3,94],"(RAI)":[4],"on":[5,14,152,162],"high-performance":[6],"embedded":[7,163],"processors":[8],"(HPEPs)":[9],"is":[10,120],"more":[11],"challenging":[12],"than":[13],"traditional":[15],"microcontroller":[16],"units":[17],"(MCUs)":[18],"or":[19],"server":[20],"processors.":[21],"Isolation-based":[22],"schemes":[23,35,176],"such":[24],"as":[25],"shadow":[26],"stacks":[27],"fail":[28],"against":[29,63],"hardware":[30,170],"memory":[31,108],"threats,":[32],"while":[33],"crypto-based":[34,57,174],"remain":[36],"vulnerable":[37],"to":[38],"forgery":[39,65],"and":[40,66,139,164,180],"replay":[41,67],"attacks.":[42],"To":[43],"the":[45,79,91,107,114,124,142,153],"challenges":[46],"of":[47],"RAI":[48,62,175],"protection":[49],"in":[50,148,177],"HPEPs,":[51],"this":[52],"article":[53],"presentsRAEnc,":[54],"a":[55,87,97,131,157],"novel":[56],"scheme,":[58],"which":[59],"provides":[60],"comprehensive":[61],"both":[64,178],"attacks":[68],"with":[69,123,168],"negligible":[70,158],"performance":[71,160],"overhead":[72,161],"via":[73],"hardware\u2013software":[74],"co-design.":[75],"We":[76,111],"first":[77],"introduce":[78],"metadata":[80],"compression":[81],"during":[82],"encryption":[85],"(MCRAE),":[86],"cryptographic":[88],"primitive":[89],"compressing":[90],"call":[92],"stack\u2019s":[93],"state":[95],"into":[96],"single,":[98],"register-resident":[99],"value":[100],"using":[101],"custom":[102],"RISC-V":[103],"instructions,":[104],"thereby":[105],"eliminating":[106],"attack":[109],"surface.":[110],"then":[112],"detail":[113],"stall-less":[115],"encryption/decryption":[116,136],"unit":[117],"(EDU)":[118],"that":[119],"tightly":[121],"coupled":[122],"processor":[125],"pipeline.":[126],"By":[127],"employing":[128],"speculative":[129],"scheduling,":[130],"low-latency":[132],"128-bit":[133],"QARMA":[134],"unit,":[135],"cache":[137],"(EDCache),":[138],"multichain":[140],"parallelism,":[141],"EDU":[143],"eliminates":[144],"pipeline":[145],"stalls":[146],"common":[147],"decoupled":[149],"accelerators.":[150],"Implemented":[151],"open-source":[154],"BOOM":[155],"processor,RAEncincurs":[156],"0.2%":[159],"SPEC":[165],"CPU2017":[166],"workloads":[167],"modest":[169],"cost,":[171],"outperforming":[172],"existing":[173],"security":[179],"performance.":[181]},"counts_by_year":[],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2026-02-03T00:00:00"}