{"id":"https://openalex.org/W7110825173","doi":"https://doi.org/10.1109/tvlsi.2025.3637272","title":"An Analytical Model of Mismatch Dominance Crossover in High-Speed Flash ADC Cores","display_name":"An Analytical Model of Mismatch Dominance Crossover in High-Speed Flash ADC Cores","publication_year":2025,"publication_date":"2025-12-09","ids":{"openalex":"https://openalex.org/W7110825173","doi":"https://doi.org/10.1109/tvlsi.2025.3637272"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2025.3637272","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3637272","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Shatadal Chatterjee","orcid":"https://orcid.org/0000-0001-7200-9993"},"institutions":[{"id":"https://openalex.org/I885392262","display_name":"GITAM University","ror":"https://ror.org/0440p1d37","country_code":"IN","type":"education","lineage":["https://openalex.org/I885392262"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shatadal Chatterjee","raw_affiliation_strings":["Department of EECE, GITAM University, Bangalore Campus, Karnataka, India"],"raw_orcid":"https://orcid.org/0000-0001-7200-9993","affiliations":[{"raw_affiliation_string":"Department of EECE, GITAM University, Bangalore Campus, Karnataka, India","institution_ids":["https://openalex.org/I885392262"]}]},{"author_position":"last","author":{"id":null,"display_name":"Jitumani Sarma","orcid":"https://orcid.org/0000-0003-4482-4493"},"institutions":[{"id":"https://openalex.org/I4210125823","display_name":"KLE University","ror":"https://ror.org/03aam9155","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210125823"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jitumani Sarma","raw_affiliation_strings":["Department of ECE, KL Deemed to be University, Guntur, India"],"raw_orcid":"https://orcid.org/0000-0003-4482-4493","affiliations":[{"raw_affiliation_string":"Department of ECE, KL Deemed to be University, Guntur, India","institution_ids":["https://openalex.org/I4210125823"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.45611398,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"2","first_page":"702","last_page":"706"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.7371000051498413,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.7371000051498413,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.06679999828338623,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.058800000697374344,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossover","display_name":"Crossover","score":0.5867000222206116},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.5552999973297119},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.5483999848365784},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.5447999835014343},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.5246000289916992},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.48750001192092896},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4530999958515167},{"id":"https://openalex.org/keywords/mean-squared-error","display_name":"Mean squared error","score":0.4424999952316284}],"concepts":[{"id":"https://openalex.org/C122507166","wikidata":"https://www.wikidata.org/wiki/Q628906","display_name":"Crossover","level":2,"score":0.5867000222206116},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.5552999973297119},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.5483999848365784},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.5447999835014343},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.5246000289916992},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5041999816894531},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.48750001192092896},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4530999958515167},{"id":"https://openalex.org/C139945424","wikidata":"https://www.wikidata.org/wiki/Q1940696","display_name":"Mean squared error","level":2,"score":0.4424999952316284},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4032999873161316},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.400299996137619},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3961000144481659},{"id":"https://openalex.org/C164862427","wikidata":"https://www.wikidata.org/wiki/Q2744647","display_name":"Flash ADC","level":4,"score":0.391400009393692},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.37950000166893005},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.34389999508857727},{"id":"https://openalex.org/C39613435","wikidata":"https://www.wikidata.org/wiki/Q846677","display_name":"Remainder","level":2,"score":0.3370000123977661},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.33090001344680786},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.31630000472068787},{"id":"https://openalex.org/C122383733","wikidata":"https://www.wikidata.org/wiki/Q865920","display_name":"Approximation error","level":2,"score":0.3100000023841858},{"id":"https://openalex.org/C2779304628","wikidata":"https://www.wikidata.org/wiki/Q3503480","display_name":"Face (sociological concept)","level":2,"score":0.3009999990463257},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28349998593330383},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.27900001406669617},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.27390000224113464},{"id":"https://openalex.org/C135692309","wikidata":"https://www.wikidata.org/wiki/Q111124","display_name":"Square (algebra)","level":2,"score":0.25850000977516174}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3637272","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3637272","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1505760695","https://openalex.org/W1672168510","https://openalex.org/W2099679337","https://openalex.org/W2140281076","https://openalex.org/W2140823559","https://openalex.org/W2758603753","https://openalex.org/W2909504354","https://openalex.org/W2970906998","https://openalex.org/W3090680032","https://openalex.org/W3101013647","https://openalex.org/W3110546428","https://openalex.org/W4205685271","https://openalex.org/W4293072295","https://openalex.org/W4294433437","https://openalex.org/W4313644165","https://openalex.org/W4386952245","https://openalex.org/W4399526416","https://openalex.org/W4412623159"],"related_works":[],"abstract_inverted_index":{"The":[0],"flash":[1],"analog-to-digital":[2],"converters":[3],"(ADCs),":[4],"essential":[5],"for":[6,30],"high-speed":[7],"embedded":[8],"systems,":[9],"face":[10],"inherent":[11],"linearity":[12],"constraints":[13],"due":[14],"to":[15,40],"device":[16],"mismatch":[17,32,58],"in":[18],"the":[19,42,76,106],"resistor":[20],"ladder":[21],"and":[22,95,105,121],"comparator":[23],"stages.":[24],"While":[25],"individual":[26],"analytical":[27,50],"models":[28],"exist":[29],"these":[31],"sources,":[33,59],"designers":[34],"rely":[35],"on":[36],"Monte":[37],"Carlo":[38],"simulations":[39],"evaluate":[41],"combined":[43],"errors.":[44],"This":[45,114],"brief":[46],"introduces":[47],"a":[48,79],"unified":[49],"framework":[51],"with":[52],"closed-form":[53],"expressions":[54],"that":[55],"capture":[56],"both":[57],"enabling":[60,127],"efficient":[61],"estimation":[62],"of":[63,84],"root":[64],"mean":[65,80],"square":[66],"(rms)":[67],"integral":[68],"nonlinearity/differential":[69],"nonlinearity":[70],"(INL/DNL).":[71],"Validated":[72],"against":[73],"circuit":[74],"simulations,":[75],"model":[77],"achieves":[78],"absolute":[81,108],"error":[82,109],"(MAE)":[83],"2.71%":[85],"(<inline-formula":[86,97],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[87,98,130],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[88,99,131],"<tex-math":[89,100,132],"notation=\"LaTeX\">$\\boldsymbol":[90],"{\\sigma":[91],"_{\\textbf":[92],"{DNL}}}$</tex-math>":[93],"</inline-formula>)":[94],"2.51%":[96],"notation=\"LaTeX\">$\\sigma":[101],"_{\\text":[102],"{INL}}$</tex-math>":[103],"</inline-formula>),":[104],"maximum":[107],"(MaxE)":[110],"remains":[111],"within":[112],"5.44%.":[113],"predictive":[115],"capability":[116],"guides":[117],"high-yield,":[118],"precision,":[119],"power,":[120],"area":[122,137],"(PPA)-optimized":[123],"system-on-chip":[124],"(SoC)":[125],"design,":[126],"over":[128],"<inline-formula":[129],"notation=\"LaTeX\">$3{\\times":[133],"}$</tex-math>":[134],"</inline-formula>":[135],"silicon":[136],"reduction":[138],"through":[139],"application-specific":[140],"optimization.":[141]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-12-10T00:00:00"}