{"id":"https://openalex.org/W7106140356","doi":"https://doi.org/10.1109/tvlsi.2025.3632677","title":"Design Space Exploration of a Unified FPGA Accelerator for Elliptic-Curve-Based Functions in Attribute-Based Encryption","display_name":"Design Space Exploration of a Unified FPGA Accelerator for Elliptic-Curve-Based Functions in Attribute-Based Encryption","publication_year":2025,"publication_date":"2025-11-20","ids":{"openalex":"https://openalex.org/W7106140356","doi":"https://doi.org/10.1109/tvlsi.2025.3632677"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2025.3632677","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3632677","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/tvlsi.2025.3632677","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Anawin Opasatian","orcid":"https://orcid.org/0009-0006-0547-4020"},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Anawin Opasatian","raw_affiliation_strings":["Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Momoko Fukuda","orcid":null},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Momoko Fukuda","raw_affiliation_strings":["Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":null,"display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.69498515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"2","first_page":"579","last_page":"592"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9700999855995178,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9700999855995178,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.006399999838322401,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10237","display_name":"Cryptography and Data Security","score":0.006200000178068876,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7562999725341797},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5691999793052673},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5299000144004822},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.48579999804496765},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.45320001244544983},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.4433000087738037},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.3930000066757202},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.38449999690055847}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7562999725341797},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.70169997215271},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5691999793052673},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5299000144004822},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.48579999804496765},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4555000066757202},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.45320001244544983},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.4433000087738037},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3970000147819519},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.3930000066757202},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.38449999690055847},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3783000111579895},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.3716000020503998},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3630000054836273},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.3479999899864197},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.326200008392334},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.32589998841285706},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.3084000051021576},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.30550000071525574},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.29429998993873596},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.2849999964237213},{"id":"https://openalex.org/C171182647","wikidata":"https://www.wikidata.org/wiki/Q126736","display_name":"Scalar multiplication","level":3,"score":0.2808000147342682},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2703000009059906},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.267300009727478},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.25380000472068787}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3632677","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3632677","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/tvlsi.2025.3632677","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3632677","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1510795740","https://openalex.org/W1531102506","https://openalex.org/W1565369953","https://openalex.org/W2069863720","https://openalex.org/W2086298846","https://openalex.org/W2108072891","https://openalex.org/W2296489817","https://openalex.org/W2307601096","https://openalex.org/W2592878255","https://openalex.org/W2603048639","https://openalex.org/W2785117529","https://openalex.org/W2797042583","https://openalex.org/W2943126371","https://openalex.org/W2947252660","https://openalex.org/W3006203549","https://openalex.org/W3007218738","https://openalex.org/W3190004108","https://openalex.org/W4210258354","https://openalex.org/W4212892091","https://openalex.org/W4213181947","https://openalex.org/W4214725836","https://openalex.org/W4243172792","https://openalex.org/W4280624543","https://openalex.org/W4288062525","https://openalex.org/W4312507664","https://openalex.org/W4386281370","https://openalex.org/W4391183605","https://openalex.org/W4391410264","https://openalex.org/W4396782831","https://openalex.org/W4399039148","https://openalex.org/W4400270590","https://openalex.org/W4401360324","https://openalex.org/W4403094465","https://openalex.org/W4403390561","https://openalex.org/W4405021843"],"related_works":[],"abstract_inverted_index":{"Attribute-based":[0],"encryption":[1],"(ABE)":[2],"requires":[3],"several":[4],"elliptic-curve-based":[5],"functions,":[6],"including":[7],"elliptic-curve":[8,134],"scalar":[9],"multiplication":[10],"(ECSM),":[11],"hashing":[12],"to":[13,86,97,157,163,195],"the":[14,68,88,99,137,141,144,167,170],"curve,":[15],"and":[16,79,108,129,131,182,189],"pairing.":[17],"Although":[18],"these":[19],"computations":[20],"share":[21],"underlying":[22],"similarities,":[23],"prior":[24],"hardware":[25],"designs":[26],"have":[27],"shown":[28],"that":[29,101],"distinct":[30],"architectures":[31],"yield":[32],"better":[33],"performance":[34,46],"for":[35,91,104],"each":[36,92],"function.":[37,93],"Consequently,":[38],"it":[39],"remains":[40],"unclear":[41],"which":[42,67],"architecture":[43],"offers":[44],"optimal":[45,145,175],"when":[47],"supporting":[48],"all":[49,178],"required":[50],"functions":[51,107,135,181],"within":[52],"a":[53,61,73,149,158],"unified":[54,171],"design.":[55],"In":[56,140,166],"this":[57],"work,":[58],"we":[59],"present":[60],"design":[62,69,77],"space":[63],"exploration":[64],"methodology":[65],"in":[66,173,190],"is":[70,84,117],"parameterized":[71],"using":[72],"defined":[74],"set":[75],"of":[76,114],"parameters,":[78],"an":[80],"automatic":[81],"schedule":[82],"generator":[83],"employed":[85],"estimate":[87],"cycle":[89],"counts":[90],"This":[94],"allows":[95],"us":[96],"identify":[98],"configuration":[100,146,176],"minimizes":[102],"latency":[103,160,185],"both":[105],"individual":[106],"complete":[109],"cryptographic":[110],"operations.":[111],"The":[112],"versatility":[113],"our":[115],"approach":[116],"demonstrated":[118],"through":[119],"two":[120],"case":[121],"studies:":[122],"1)":[123],"ECSM":[124],"over":[125,136],"Curve25519,":[126],"Secp256k1,":[127],"NIST-P256,":[128],"NIST-P384;":[130],"2)":[132],"multiple":[133],"BLS12-381":[138],"curve.":[139],"first":[142],"case,":[143,169],"implemented":[147],"on":[148],"Virtex7":[150],"field-programmable":[151],"gate":[152],"array":[153],"(FPGA)":[154],"achieves":[155,183],"up":[156],"15%":[159],"reduction":[161],"compared":[162,194],"state-of-the-art":[164],"designs.":[165,197],"second":[168],"accelerator":[172],"its":[174],"supports":[177],"core":[179],"ABE":[180],"superior":[184],"or":[186],"throughput-per-area":[187],"(TPA),":[188],"some":[191],"cases":[192],"both,":[193],"existing":[196]},"counts_by_year":[],"updated_date":"2026-01-25T23:04:38.658462","created_date":"2025-11-20T00:00:00"}
