{"id":"https://openalex.org/W7104655280","doi":"https://doi.org/10.1109/tvlsi.2025.3627560","title":"A Crosstalk Suppressed Reconfigurable Fully Passive Multichannel Noise-Shaping SAR ADC","display_name":"A Crosstalk Suppressed Reconfigurable Fully Passive Multichannel Noise-Shaping SAR ADC","publication_year":2025,"publication_date":"2025-11-11","ids":{"openalex":"https://openalex.org/W7104655280","doi":"https://doi.org/10.1109/tvlsi.2025.3627560"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2025.3627560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3627560","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Yu Lu","orcid":"https://orcid.org/0009-0001-8536-6321"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yu Lu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0001-8536-6321","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Pengfei Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Pengfei Jiang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Qingsong Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qingsong Zhang","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Tianyue Sun","orcid":"https://orcid.org/0009-0002-8762-4328"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianyue Sun","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0002-8762-4328","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Wenjun Gong","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wenjun Gong","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yuxin Liao","orcid":"https://orcid.org/0009-0004-3232-5421"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuxin Liao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0004-3232-5421","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":null,"display_name":"Hao Min","orcid":"https://orcid.org/0000-0002-5673-1115"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Min","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5673-1115","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, School of Microelectronics, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067","https://openalex.org/I4210132426"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.48041451,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"2","first_page":"682","last_page":"686"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.8115000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.8115000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.12120000272989273,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.013899999670684338,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.5575000047683716},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.527400016784668},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.5260999798774719},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.43549999594688416},{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.36910000443458557},{"id":"https://openalex.org/keywords/automatic-gain-control","display_name":"Automatic gain control","score":0.36660000681877136},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.35499998927116394},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.32589998841285706},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.31279999017715454},{"id":"https://openalex.org/keywords/predistortion","display_name":"Predistortion","score":0.3111000061035156}],"concepts":[{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.7026000022888184},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.5575000047683716},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.527400016784668},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.5260999798774719},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5009999871253967},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.43549999594688416},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.4146000146865845},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.36910000443458557},{"id":"https://openalex.org/C177502760","wikidata":"https://www.wikidata.org/wiki/Q782524","display_name":"Automatic gain control","level":4,"score":0.36660000681877136},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.35499998927116394},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.32589998841285706},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.31279999017715454},{"id":"https://openalex.org/C2778587875","wikidata":"https://www.wikidata.org/wiki/Q7239686","display_name":"Predistortion","level":4,"score":0.3111000061035156},{"id":"https://openalex.org/C65165936","wikidata":"https://www.wikidata.org/wiki/Q575784","display_name":"Baseband","level":3,"score":0.30309998989105225},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.29170000553131104},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.2888999879360199},{"id":"https://openalex.org/C50151734","wikidata":"https://www.wikidata.org/wiki/Q1759577","display_name":"Matched filter","level":3,"score":0.2879999876022339},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2840999960899353},{"id":"https://openalex.org/C11210021","wikidata":"https://www.wikidata.org/wiki/Q1520713","display_name":"Linearization","level":3,"score":0.28349998593330383},{"id":"https://openalex.org/C2776096036","wikidata":"https://www.wikidata.org/wiki/Q1140483","display_name":"Narrowband","level":2,"score":0.28130000829696655},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.27869999408721924},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.2784999907016754},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.2736999988555908},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.2687999904155731},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.2680000066757202},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.2669000029563904},{"id":"https://openalex.org/C121308736","wikidata":"https://www.wikidata.org/wiki/Q149918","display_name":"Communications satellite","level":3,"score":0.26579999923706055},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.2605000138282776},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2599000036716461},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.2565999925136566},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.25450000166893005}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3627560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3627560","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W605564925","https://openalex.org/W2093986961","https://openalex.org/W2741408477","https://openalex.org/W2901171969","https://openalex.org/W3002516890","https://openalex.org/W3062176931","https://openalex.org/W3174559553","https://openalex.org/W3193784424","https://openalex.org/W4324116441","https://openalex.org/W4362500660","https://openalex.org/W4383899732","https://openalex.org/W4387129561","https://openalex.org/W4400231107"],"related_works":[],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"a":[3,53,87,94],"reconfigurable":[4],"multichannel":[5,56],"noise-shaping":[6],"(NS)":[7],"SAR":[8],"analog-to-digital":[9],"converter":[10],"(ADC)":[11],"with":[12,32,93,119],"crosstalk":[13,54],"suppression.":[14],"All":[15],"nonmemory":[16],"blocks":[17],"are":[18,114],"multiplexed":[19],"among":[20],"all":[21,123],"channels":[22,125],"assisted":[23],"by":[24],"the":[25,43,79],"proposed":[26],"timing":[27],"control":[28],"scheme,":[29],"enabling":[30],"reconfiguration":[31],"negligible":[33],"power":[34],"and":[35,52,108,116,128],"hardware":[36],"cost.":[37],"A":[38,67],"novel":[39],"approach":[40],"to":[41,77],"determine":[42],"design":[44],"parameters":[45],"of":[46,81,90,105],"nonideal":[47],"loop":[48,59],"filters":[49],"is":[50,61,74],"proposed,":[51],"suppressed":[55],"fully":[57],"passive":[58],"filter":[60],"developed":[62],"based":[63],"on":[64],"this":[65],"method.":[66],"memoryless":[68],"binary":[69],"dynamic":[70],"element":[71],"matching":[72],"(DEM)":[73],"also":[75],"adopted":[76],"suppress":[78],"nonlinearity":[80],"each":[82],"channel.":[83],"The":[84],"ADC":[85],"achieves":[86],"typical":[88,102],"SNDR":[89],"77.49/72.17/66.62":[91],"dB":[92,118],"20-kHz":[95],"bandwidth":[96],"under":[97,126],"one-/two-/four-channel":[98],"modes,":[99],"respectively,":[100],"realizing":[101],"Schreier":[103],"FoMs":[104],"169.54,":[106],"167.20,":[107],"164.64":[109],"dB.":[110],"Averaged":[111],"interchannel":[112],"crosstalks":[113],"\u221279.17":[115],"\u221277.37":[117],"\u22122.5-dBFS":[120],"inputs":[121],"in":[122],"input":[124],"two-":[127],"four-channel":[129],"modes.":[130]},"counts_by_year":[],"updated_date":"2026-01-25T23:04:38.658462","created_date":"2025-11-11T00:00:00"}
