{"id":"https://openalex.org/W7104687125","doi":"https://doi.org/10.1109/tvlsi.2025.3625215","title":"12-bit SAR ADC Employing a 9-bit CDAC in Vanilla CMOS 40-nm Technology","display_name":"12-bit SAR ADC Employing a 9-bit CDAC in Vanilla CMOS 40-nm Technology","publication_year":2025,"publication_date":"2025-11-11","ids":{"openalex":"https://openalex.org/W7104687125","doi":"https://doi.org/10.1109/tvlsi.2025.3625215"},"language":null,"primary_location":{"id":"doi:10.1109/tvlsi.2025.3625215","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3625215","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Amr W. Hassan","orcid":"https://orcid.org/0000-0003-1356-4254"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Amr W. Hassan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&#x26;M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&#x26;M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Shangfeng Qiu","orcid":"https://orcid.org/0000-0001-6938-9083"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shangfeng Qiu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&#x26;M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&#x26;M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"last","author":{"id":null,"display_name":"Jose Silva-Martinez","orcid":"https://orcid.org/0000-0002-7960-0177"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jose Silva-Martinez","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Texas A&#x26;M University, College Station, TX, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Texas A&#x26;M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91045830"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.49294828,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":"2","first_page":"352","last_page":"365"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9891999959945679,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.002400000113993883,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12300","display_name":"Advanced Electrical Measurement Techniques","score":0.0010999999940395355,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.7541999816894531},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6972000002861023},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6212000250816345},{"id":"https://openalex.org/keywords/capacitive-sensing","display_name":"Capacitive sensing","score":0.492900013923645},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.45680001378059387},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.39750000834465027},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3779999911785126}],"concepts":[{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.7541999816894531},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6972000002861023},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6212000250816345},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5838000178337097},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.492900013923645},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.45680001378059387},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4077000021934509},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.39750000834465027},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38609999418258667},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.38190001249313354},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3779999911785126},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.37540000677108765},{"id":"https://openalex.org/C142311740","wikidata":"https://www.wikidata.org/wiki/Q1066177","display_name":"Shaping","level":2,"score":0.32580000162124634},{"id":"https://openalex.org/C44351266","wikidata":"https://www.wikidata.org/wiki/Q1465532","display_name":"Voltage reference","level":3,"score":0.30889999866485596},{"id":"https://openalex.org/C13355873","wikidata":"https://www.wikidata.org/wiki/Q2920850","display_name":"Connection (principal bundle)","level":2,"score":0.3041999936103821},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.2980000078678131},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2903999984264374},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.29010000824928284},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.2858999967575073}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3625215","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3625215","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.45645204186439514}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1526838648","https://openalex.org/W1977030506","https://openalex.org/W1999118881","https://openalex.org/W2032346897","https://openalex.org/W2100749576","https://openalex.org/W2101004723","https://openalex.org/W2138134203","https://openalex.org/W2154979280","https://openalex.org/W2306739649","https://openalex.org/W2541421006","https://openalex.org/W2564345649","https://openalex.org/W2593067874","https://openalex.org/W2743851166","https://openalex.org/W2744970705","https://openalex.org/W2760245843","https://openalex.org/W2921837375","https://openalex.org/W2922215933","https://openalex.org/W2980833659","https://openalex.org/W3011878475","https://openalex.org/W3121152720","https://openalex.org/W4226432265","https://openalex.org/W4360606296","https://openalex.org/W4387831768","https://openalex.org/W4414229250"],"related_works":[],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,15,37,46,71,80,117,134],"130-MS/s":[4],"successive":[5],"approximation":[6],"register":[7],"(SAR)":[8],"analog-to-digital":[9],"converter":[10],"(ADC)":[11],"architecture":[12,111,154],"that":[13,23,104],"uses":[14],"9-bit":[16],"capacitive":[17],"DAC":[18],"(CDAC)":[19],"and":[20,32],"innovative":[21],"techniques":[22],"include":[24],"passive":[25,53],"amplification":[26,54],"circuitry":[27],"without":[28],"engaging":[29],"active":[30,98,141],"components":[31],"the":[33,59,64,85,90,97,105,108,122,139,159],"strategic":[34],"connection":[35],"of":[36,48,58,96,107,162],"unity":[38],"capacitor":[39],"to":[40,44,70],"multiple":[41],"reference":[42,77],"voltages,":[43],"achieve":[45],"total":[47],"12":[49],"bits.":[50],"The":[51,100],"proposed":[52,91,109,123],"technique":[55],"saves":[56,93],"27%":[57],"ADC":[60,110,124],"area":[61,142],"through":[62],"reducing":[63],"CDAC":[65,74],"size":[66],"by":[67],"50%":[68],"compared":[69],"conventional":[72,86],"10-bit":[73],"+2-bit":[75],"voltage":[76],"design":[78],"for":[79,133],"12-bit":[81,87],"resolution.":[82],"Compared":[83],"with":[84],"C-DAC":[88],"SAR,":[89],"SAR-ADC":[92],"over":[94],"75%":[95],"area.":[99],"measurement":[101],"results":[102,157],"reveal":[103],"core":[106],"dissipates":[112],"3":[113],"mW.":[114],"Fabricated":[115],"in":[116],"mainstream":[118],"40-nm":[119],"CMOS":[120],"technology,":[121],"attains":[125],"SNDR/SFDR":[126],"ratios":[127],"as":[128,130],"high":[129],"63.5/72.13":[131],"dB":[132,172],"10-MHz":[135],"sinusoidal":[136],"test":[137],"tone;":[138],"SAR":[140],"is":[143],"about":[144],"<inline-formula":[145],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[146],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[147],"<tex-math":[148],"notation=\"LaTeX\">$0.00966~\\text":[149],"{mm}^{2}$</tex-math>":[150],"</inline-formula>.":[151],"Furthermore,":[152],"this":[153],"yields":[155],"favorable":[156],"regarding":[158],"Walden":[160],"figure-of-merit":[161],"approximately":[163],"26.5":[164],"fJ/conv-step":[165],"while":[166],"maintaining":[167],"Schreier":[168],"FOM":[169],"around":[170],"165.37":[171],"when":[173],"measured":[174],"at":[175],"10":[176],"MHz.":[177]},"counts_by_year":[],"updated_date":"2026-01-25T23:04:38.658462","created_date":"2025-11-11T00:00:00"}