{"id":"https://openalex.org/W4414908203","doi":"https://doi.org/10.1109/tvlsi.2025.3615468","title":"A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures","display_name":"A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures","publication_year":2025,"publication_date":"2025-10-07","ids":{"openalex":"https://openalex.org/W4414908203","doi":"https://doi.org/10.1109/tvlsi.2025.3615468"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3615468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3615468","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062370793","display_name":"Sunrui Zhang","orcid":"https://orcid.org/0009-0000-9539-1427"},"institutions":[{"id":"https://openalex.org/I4210128628","display_name":"Peking University Shenzhen Hospital","ror":"https://ror.org/03kkjyb15","country_code":"CN","type":"healthcare","lineage":["https://openalex.org/I4210128628"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Sunrui Zhang","raw_affiliation_strings":["Peking University Shenzhen Graduate School, Shenzhen, China"],"raw_orcid":"https://orcid.org/0009-0000-9539-1427","affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I4210128628"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050097039","display_name":"Xiaole Cui","orcid":"https://orcid.org/0000-0002-3382-3703"},"institutions":[{"id":"https://openalex.org/I4210128628","display_name":"Peking University Shenzhen Hospital","ror":"https://ror.org/03kkjyb15","country_code":"CN","type":"healthcare","lineage":["https://openalex.org/I4210128628"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaole Cui","raw_affiliation_strings":["Peking University Shenzhen Graduate School, Shenzhen, China"],"raw_orcid":"https://orcid.org/0000-0002-3382-3703","affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I4210128628"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039314767","display_name":"Feng Wei","orcid":"https://orcid.org/0000-0002-7676-7596"},"institutions":[{"id":"https://openalex.org/I4210128628","display_name":"Peking University Shenzhen Hospital","ror":"https://ror.org/03kkjyb15","country_code":"CN","type":"healthcare","lineage":["https://openalex.org/I4210128628"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Feng Wei","raw_affiliation_strings":["Peking University Shenzhen Graduate School, Shenzhen, China"],"raw_orcid":"https://orcid.org/0000-0002-7676-7596","affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School, Shenzhen, China","institution_ids":["https://openalex.org/I4210128628"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100399117","display_name":"Xing Zhang","orcid":"https://orcid.org/0000-0002-2699-3448"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xing Zhang","raw_affiliation_strings":["Institute of Microelectronics, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.4756,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.92994408,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":96},"biblio":{"volume":"34","issue":"1","first_page":"280","last_page":"293"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.7864000201225281},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.6883000135421753},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6238999962806702},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5498999953269958},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.5382999777793884},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.501800000667572},{"id":"https://openalex.org/keywords/fibonacci-number","display_name":"Fibonacci number","score":0.43860000371932983},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4034000039100647},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.3961000144481659}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.7864000201225281},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.6883000135421753},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6238999962806702},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5867999792098999},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5498999953269958},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5382999777793884},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.501800000667572},{"id":"https://openalex.org/C173734053","wikidata":"https://www.wikidata.org/wiki/Q47577","display_name":"Fibonacci number","level":2,"score":0.43860000371932983},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4034000039100647},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.3961000144481659},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3953999876976013},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.38929998874664307},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3824000060558319},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.35010001063346863},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.33889999985694885},{"id":"https://openalex.org/C159862308","wikidata":"https://www.wikidata.org/wiki/Q681101","display_name":"Linear feedback shift register","level":4,"score":0.3368000090122223},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.3345000147819519},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30820000171661377},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.30149999260902405},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.29789999127388},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2971999943256378},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2824999988079071},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2824000120162964},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27489998936653137},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.27410000562667847},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.2720000147819519},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.26489999890327454},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2648000121116638},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.26159998774528503}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3615468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3615468","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4484392832","display_name":null,"funder_award_id":"92373206","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5218122100","display_name":null,"funder_award_id":"2024YFB3614200","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1529264663","https://openalex.org/W1595368737","https://openalex.org/W1667843264","https://openalex.org/W1979092306","https://openalex.org/W1999085092","https://openalex.org/W2071347611","https://openalex.org/W2097270518","https://openalex.org/W2117207900","https://openalex.org/W2606722458","https://openalex.org/W2914256504","https://openalex.org/W2976137532","https://openalex.org/W2981537656","https://openalex.org/W3005157299","https://openalex.org/W3014325818","https://openalex.org/W3087197968","https://openalex.org/W3092601938","https://openalex.org/W3128966520","https://openalex.org/W3134925155","https://openalex.org/W3135906938","https://openalex.org/W3139521791","https://openalex.org/W3185896771","https://openalex.org/W3189313959","https://openalex.org/W4220785886","https://openalex.org/W4296704807","https://openalex.org/W4312611881","https://openalex.org/W4312627759","https://openalex.org/W4312715812","https://openalex.org/W4379806350","https://openalex.org/W4384026345","https://openalex.org/W4387129467","https://openalex.org/W4388626384","https://openalex.org/W4388666846","https://openalex.org/W4391407189","https://openalex.org/W4392114388","https://openalex.org/W4400899028","https://openalex.org/W4404564564","https://openalex.org/W4406727937","https://openalex.org/W4409494706"],"related_works":[],"abstract_inverted_index":{"Digital":[0],"static":[1],"random":[2],"access":[3],"memory-based":[4],"in-memory":[5],"computing":[6],"(SRAM-IMC)":[7],"is":[8,49,234],"a":[9,24,118],"promising":[10],"computation":[11],"paradigm":[12],"to":[13,97,178],"break":[14],"the":[15,19,32,42,47,50,56,61,66,74,81,88,91,106,111,125,130,135,140,151,156,172,180,191,201,204,225,230],"von-Neumann":[16],"bottleneck.":[17],"However,":[18],"IMC":[20,131],"architectures":[21],"also":[22],"bring":[23],"series":[25],"of":[26,31,46,52,65],"challenges":[27,48],"for":[28,124],"testing,":[29],"because":[30,60],"circuit":[33],"structures":[34],"and":[35,90,133,145,163,171,183,203,236],"operations":[36],"that":[37,190],"do":[38],"not":[39],"exist":[40],"in":[41,55],"conventional":[43,82,226],"memories.":[44],"One":[45],"testing":[51],"evaluation":[53,67,126,187],"circuits":[54,68],"digital":[57],"SRAM-IMC":[58],"architectures,":[59],"primary":[62],"inputs":[63],"(PIs)":[64],"cannot":[69],"be":[70],"directly":[71],"accessed":[72],"by":[73],"testers.":[75],"Several":[76],"test":[77,93,108,181,197,206,214],"approaches":[78],"such":[79],"as":[80],"logic":[83],"built-in":[84,120],"self-test":[85,121],"(LBIST)":[86],"modules,":[87],"indirect":[89,202],"scan-chain-based":[92,205],"methods":[94],"are":[95,176],"proposed":[96,136,192,209,231],"address":[98],"this":[99],"issue.":[100],"Nevertheless,":[101],"these":[102],"solutions":[103],"suffer":[104],"from":[105],"low":[107],"performance":[109,198],"or":[110],"high":[112],"area":[113,221],"consumption.":[114],"This":[115],"work":[116],"proposes":[117],"reconfigurable":[119],"(BIST)":[122],"scheme":[123,138,194,211,233],"circuits.":[127],"By":[128],"reusing":[129],"bitcells":[132],"operations,":[134],"BIST":[137,193,210,232],"implements":[139],"separate":[141],"pattern":[142,153],"generation":[143],"(PG)":[144],"response":[146],"analysis":[147],"(RA)":[148],"processes.":[149],"Furthermore,":[150],"diverse":[152],"generators,":[154],"including":[155],"Fibonacci":[157],"linear":[158],"feedback":[159,169],"shift":[160],"register":[161],"(LFSR)":[162],"weighted":[164],"LFSR":[165],"(WLFSR)":[166],"with":[167,200,224],"adjustable":[168],"polynomials":[170],"cellular":[173],"automata":[174],"(CA),":[175],"realized":[177],"improve":[179],"efficiency":[182],"fault":[184],"coverage.":[185],"The":[186,208],"results":[188],"show":[189],"has":[195,212,218],"better":[196],"comparing":[199,223],"approaches.":[207],"comparable":[213],"performance,":[215],"whereas":[216],"it":[217],"much":[219],"less":[220],"overhead":[222],"LBIST":[227],"schemes.":[228],"Additionally,":[229],"testable":[235],"repairable.":[237]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}