{"id":"https://openalex.org/W4414908341","doi":"https://doi.org/10.1109/tvlsi.2025.3614568","title":"NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing","display_name":"NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing","publication_year":2025,"publication_date":"2025-10-07","ids":{"openalex":"https://openalex.org/W4414908341","doi":"https://doi.org/10.1109/tvlsi.2025.3614568"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3614568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3614568","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072439444","display_name":"Aibin Yan","orcid":"https://orcid.org/0000-0003-0024-987X"},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Aibin Yan","raw_affiliation_strings":["School of Microelectronics, Hefei University of Technology, Hefei, China"],"raw_orcid":"https://orcid.org/0000-0003-0024-987X","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100333647","display_name":"Yue Zhang","orcid":"https://orcid.org/0000-0001-6893-7199"},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yue Zhang","raw_affiliation_strings":["School of Microelectronics, Hefei University of Technology, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100716059","display_name":"Litao Wang","orcid":"https://orcid.org/0000-0002-3734-6676"},"institutions":[{"id":"https://openalex.org/I143868143","display_name":"Anhui University","ror":"https://ror.org/05th6yx34","country_code":"CN","type":"education","lineage":["https://openalex.org/I143868143"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Litao Wang","raw_affiliation_strings":["School of Computer Science and Technology, Anhui University, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Technology, Anhui University, Hefei, China","institution_ids":["https://openalex.org/I143868143"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073810494","display_name":"Zhengfeng Huang","orcid":"https://orcid.org/0000-0001-8695-4478"},"institutions":[{"id":"https://openalex.org/I16365422","display_name":"Hefei University of Technology","ror":"https://ror.org/02czkny70","country_code":"CN","type":"education","lineage":["https://openalex.org/I16365422"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhengfeng Huang","raw_affiliation_strings":["School of Microelectronics, Hefei University of Technology, Hefei, China"],"raw_orcid":"https://orcid.org/0000-0001-8695-4478","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Hefei University of Technology, Hefei, China","institution_ids":["https://openalex.org/I16365422"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101571504","display_name":"Qingyang Zhang","orcid":"https://orcid.org/0000-0001-7396-874X"},"institutions":[{"id":"https://openalex.org/I143868143","display_name":"Anhui University","ror":"https://ror.org/05th6yx34","country_code":"CN","type":"education","lineage":["https://openalex.org/I143868143"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qingyang Zhang","raw_affiliation_strings":["School of Computer Science and Technology, Anhui University, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Technology, Anhui University, Hefei, China","institution_ids":["https://openalex.org/I143868143"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085987622","display_name":"Tianming Ni","orcid":"https://orcid.org/0000-0001-6272-8660"},"institutions":[{"id":"https://openalex.org/I70908550","display_name":"Anhui Polytechnic University","ror":"https://ror.org/041sj0284","country_code":"CN","type":"education","lineage":["https://openalex.org/I70908550"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianming Ni","raw_affiliation_strings":["School of Integrated Circuits, Anhui Polytechnic University, Wuhu, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Anhui Polytechnic University, Wuhu, China","institution_ids":["https://openalex.org/I70908550"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005116115","display_name":"Patrick Girard","orcid":"https://orcid.org/0000-0003-0722-8772"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Patrick Girard","raw_affiliation_strings":["LIRMM, CNRS, University of Montpellier, Montpellier, France"],"raw_orcid":"https://orcid.org/0000-0003-0722-8772","affiliations":[{"raw_affiliation_string":"LIRMM, CNRS, University of Montpellier, Montpellier, France","institution_ids":["https://openalex.org/I4210101743","https://openalex.org/I19894307","https://openalex.org/I1294671590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084697545","display_name":"Xiaoqing Wen","orcid":"https://orcid.org/0000-0001-8305-604X"},"institutions":[{"id":"https://openalex.org/I207014233","display_name":"Kyushu Institute of Technology","ror":"https://ror.org/02278tr80","country_code":"JP","type":"education","lineage":["https://openalex.org/I207014233"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Xiaoqing Wen","raw_affiliation_strings":["Department of Computer Science and Networks, Kyushu Institute of Technology, Fukuoka, Japan"],"raw_orcid":"https://orcid.org/0000-0001-8305-604X","affiliations":[{"raw_affiliation_string":"Department of Computer Science and Networks, Kyushu Institute of Technology, Fukuoka, Japan","institution_ids":["https://openalex.org/I207014233"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.377,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.82591982,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"34","issue":"1","first_page":"268","last_page":"279"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9936000108718872,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6549000144004822},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5591999888420105},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.47429999709129333},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4553000032901764},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.44769999384880066},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3407000005245209},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.3407000005245209},{"id":"https://openalex.org/keywords/compatibility","display_name":"Compatibility (geochemistry)","score":0.335099995136261},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.33230000734329224}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6549000144004822},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5591999888420105},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5027999877929688},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4862000048160553},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.47429999709129333},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4553000032901764},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.44769999384880066},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.41269999742507935},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40700000524520874},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3653999865055084},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.3407000005245209},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3407000005245209},{"id":"https://openalex.org/C2778648169","wikidata":"https://www.wikidata.org/wiki/Q967768","display_name":"Compatibility (geochemistry)","level":2,"score":0.335099995136261},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.33230000734329224},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.3287000060081482},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3018999993801117},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.29679998755455017},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.2953999936580658},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.29420000314712524},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.2818000018596649},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.2718000113964081},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.2669999897480011},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.26170000433921814},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.26159998774528503},{"id":"https://openalex.org/C129014197","wikidata":"https://www.wikidata.org/wiki/Q906544","display_name":"Power semiconductor device","level":3,"score":0.25760000944137573},{"id":"https://openalex.org/C2989121073","wikidata":"https://www.wikidata.org/wiki/Q1309019","display_name":"Transient analysis","level":3,"score":0.2565000057220459}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2025.3614568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3614568","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:HAL:lirmm-05306535v1","is_oa":false,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-05306535","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2026, 34 (1), pp.268-279. ⟨10.1109/TVLSI.2025.3614568⟩","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5551567736","display_name":null,"funder_award_id":"2208085J02","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7890569886","display_name":null,"funder_award_id":"2022AH010059","funder_id":"https://openalex.org/F4320330356","funder_display_name":"Distinguished Young Scholar Foundation of Hunan Province"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320330356","display_name":"Distinguished Young Scholar Foundation of Hunan Province","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Soft":[0],"errors":[1],"and":[2,12,34,55,62,91,100,116],"power":[3],"dissipation":[4],"emerge":[5],"as":[6],"critical":[7],"challenges":[8],"in":[9,108],"developing":[10],"high-reliability":[11],"cost-sensitive":[13],"embedded":[14],"systems.":[15],"To":[16],"address":[17],"these":[18],"issues,":[19],"the":[20,105,120],"magnetic":[21],"tunnel":[22],"junction":[23],"(MTJ)":[24],"is":[25],"considered":[26],"a":[27,47,74,81],"promising":[28],"solution":[29],"due":[30],"to":[31],"its":[32,35],"nonvolatility":[33,61],"compatibility":[36],"with":[37,80],"traditional":[38],"CMOS":[39,79],"manufacturing":[40],"processes.":[41],"In":[42],"this":[43],"work,":[44],"we":[45],"propose":[46],"novel":[48],"nonvolatile":[49],"(NV)":[50],"latch":[51],"consisting":[52],"of":[53,110,119],"inverters":[54],"MTJs,":[56],"namely,":[57],"NVLIM,":[58],"which":[59],"provides":[60],"robust":[63,112],"partial":[64,113],"tolerance":[65],"against":[66],"triple-node-upsets":[67],"(TNUs)":[68],"at":[69],"low":[70],"cost.":[71],"NVLIM":[72],"integrates":[73],"TNU-tolerant":[75],"block":[76,83],"based":[77],"on":[78],"backup-restore":[82],"using":[84],"MTJs.":[85],"Simulation":[86],"results":[87],"incorporating":[88],"process,":[89],"voltage,":[90],"temperature":[92,96],"(PVT)":[93],"variations,":[94],"bias":[95],"instability":[97],"(BTI)":[98],"impact,":[99],"Monte":[101],"Carlo":[102],"simulations":[103],"demonstrate":[104],"balanced":[106],"performance":[107],"terms":[109],"nonvolatility,":[111],"TNU":[114],"tolerance,":[115],"comprehensive":[117],"overhead":[118],"proposed":[121],"latch.":[122]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}