{"id":"https://openalex.org/W6884627359","doi":"https://doi.org/10.1109/tvlsi.2025.3583289","title":"IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems","display_name":"IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems","publication_year":2025,"publication_date":"2025-07-10","ids":{"openalex":"https://openalex.org/W6884627359","doi":"https://doi.org/10.1109/tvlsi.2025.3583289"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3583289","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3583289","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Jinming Zhang","orcid":"https://orcid.org/0000-0002-9353-5447"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinming Zhang","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-9353-5447","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Zhihong Chen","orcid":"https://orcid.org/0009-0007-2318-2619"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhihong Chen","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0009-0007-2318-2619","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yaoyao Ye","orcid":"https://orcid.org/0000-0003-0022-228X"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yaoyao Ye","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0003-0022-228X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Hao Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hao Chen","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Xiao Han","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiao Han","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jianfei Jiang","orcid":"https://orcid.org/0000-0002-5521-6197"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfei Jiang","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5521-6197","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Weiguang Sheng","orcid":"https://orcid.org/0000-0002-7831-526X"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiguang Sheng","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-7831-526X","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ningyi Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ningyi Xu","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yong Lian","orcid":"https://orcid.org/0000-0002-5289-5219"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yong Lian","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-5289-5219","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":null,"display_name":"Guanghui He","orcid":"https://orcid.org/0000-0002-0486-6421"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guanghui He","raw_affiliation_strings":["State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0002-0486-6421","affiliations":[{"raw_affiliation_string":"State Key Laboratory of Micro/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.9389,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.82914726,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"33","issue":"9","first_page":"2424","last_page":"2437"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9320999979972839,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9320999979972839,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.03880000114440918,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.010200000368058681,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.8145999908447266},{"id":"https://openalex.org/keywords/deadlock-prevention-algorithms","display_name":"Deadlock prevention algorithms","score":0.6323999762535095},{"id":"https://openalex.org/keywords/virtual-channel","display_name":"Virtual channel","score":0.5960000157356262},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5608999729156494},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4860999882221222},{"id":"https://openalex.org/keywords/dependency-graph","display_name":"Dependency graph","score":0.43059998750686646},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.39590001106262207},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.3555000126361847}],"concepts":[{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.8145999908447266},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.738099992275238},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.6604999899864197},{"id":"https://openalex.org/C113429609","wikidata":"https://www.wikidata.org/wiki/Q4060699","display_name":"Deadlock prevention algorithms","level":3,"score":0.6323999762535095},{"id":"https://openalex.org/C2777076873","wikidata":"https://www.wikidata.org/wiki/Q2291875","display_name":"Virtual channel","level":3,"score":0.5960000157356262},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5608999729156494},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4860999882221222},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.4839000105857849},{"id":"https://openalex.org/C16311509","wikidata":"https://www.wikidata.org/wiki/Q4148050","display_name":"Dependency graph","level":3,"score":0.43059998750686646},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.39590001106262207},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.3555000126361847},{"id":"https://openalex.org/C19768560","wikidata":"https://www.wikidata.org/wiki/Q320727","display_name":"Dependency (UML)","level":2,"score":0.3463999927043915},{"id":"https://openalex.org/C84511453","wikidata":"https://www.wikidata.org/wiki/Q2914952","display_name":"Concurrency control","level":3,"score":0.3059000074863434},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.3018999993801117},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.29330000281333923},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.2883000075817108},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.28279998898506165},{"id":"https://openalex.org/C113508815","wikidata":"https://www.wikidata.org/wiki/Q193446","display_name":"Packet switching","level":3,"score":0.2815000116825104},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.26759999990463257},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.26669999957084656},{"id":"https://openalex.org/C134448949","wikidata":"https://www.wikidata.org/wiki/Q1384274","display_name":"Expediting","level":2,"score":0.2653999924659729},{"id":"https://openalex.org/C54108766","wikidata":"https://www.wikidata.org/wiki/Q391064","display_name":"Packet loss","level":3,"score":0.2621999979019165},{"id":"https://openalex.org/C203274722","wikidata":"https://www.wikidata.org/wiki/Q7001161","display_name":"Network performance","level":2,"score":0.26030001044273376}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3583289","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3583289","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G100274347","display_name":null,"funder_award_id":"25ZR1402272","funder_id":"https://openalex.org/F4320309612","funder_display_name":"Natural Science Foundation of Shanghai"},{"id":"https://openalex.org/G5227578763","display_name":null,"funder_award_id":"92464302","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320309612","display_name":"Natural Science Foundation of Shanghai","ror":null},{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W2019275594","https://openalex.org/W2095795217","https://openalex.org/W2144476064","https://openalex.org/W2154323564","https://openalex.org/W2166772458","https://openalex.org/W2179513480","https://openalex.org/W2344873464","https://openalex.org/W2518432791","https://openalex.org/W2612262733","https://openalex.org/W2884166449","https://openalex.org/W2884810594","https://openalex.org/W2898566692","https://openalex.org/W2979714411","https://openalex.org/W2999356938","https://openalex.org/W3006667757","https://openalex.org/W3017153815","https://openalex.org/W3080132014","https://openalex.org/W3094554961","https://openalex.org/W3099119422","https://openalex.org/W3108101844","https://openalex.org/W3111684448","https://openalex.org/W3148326493","https://openalex.org/W3209605964","https://openalex.org/W4235172414","https://openalex.org/W4280494913","https://openalex.org/W4280498518","https://openalex.org/W4280644295","https://openalex.org/W4293023438","https://openalex.org/W4296209134","https://openalex.org/W4360831793","https://openalex.org/W4386280941","https://openalex.org/W4391827236","https://openalex.org/W4393140944","https://openalex.org/W4396817352","https://openalex.org/W4399487283","https://openalex.org/W4400314928","https://openalex.org/W4402570070","https://openalex.org/W4405513857"],"related_works":[],"abstract_inverted_index":{"Large-area":[0],"chips":[1],"using":[2],"advanced":[3],"processes":[4],"are":[5,190],"facing":[6],"challenges":[7],"in":[8,13,149,160,216],"yield":[9,29],"rate":[10],"and":[11,28,51,140,176],"limitations":[12],"lithographic":[14],"area.":[15],"Chiplet":[16],"technology":[17],"has":[18],"emerged":[19],"as":[20],"a":[21,93,122,142,210],"promising":[22],"solution":[23],"with":[24,202,227],"improved":[25],"flexibility,":[26],"scalability,":[27],"rate.":[30],"However,":[31],"even":[32],"if":[33],"each":[34,55,150],"chiplet":[35],"is":[36,65,214],"internally":[37],"deadlock-free,":[38],"the":[39,48,66,88,129,134,161,170,178,193,220,228,238],"inter-chiplet":[40,63,77,85,89,130,166],"network":[41,186],"may":[42],"still":[43],"encounter":[44],"deadlock":[45,79,117,123,171,200],"issues.":[46],"Ensuring":[47],"modular":[49],"design":[50,197],"topology":[52],"agnostic":[53],"of":[54,69,180,223,240],"chiplet,":[56],"while":[57],"achieving":[58],"better":[59],"performance":[60,113,204],"under":[61],"limited":[62],"bandwidth,":[64],"main":[67],"challenge":[68],"routing":[70],"algorithms.":[71],"This":[72,196],"article":[73],"introduces":[74],"IPDR,":[75],"an":[76,165],"priority-driven":[78],"resolution":[80,201],"mechanism":[81],"specifically":[82],"designed":[83],"for":[84],"networks,":[86],"where":[87],"link":[90],"often":[91],"constitutes":[92],"critical":[94],"system":[95],"bottleneck.":[96],"IPDR":[97,127,144,147,217,232],"imposes":[98],"no":[99],"restrictions":[100],"on":[101],"virtual":[102,185],"channel":[103],"(VC)":[104],"allocation":[105],"or":[106],"turn":[107],"strategies":[108],"during":[109,164,183,206],"normal":[110],"state,":[111],"avoiding":[112],"penalties":[114],"from":[115],"conservative":[116],"avoidance":[118],"methods.":[119],"Upon":[120],"detecting":[121],"at":[124,155,237],"boundary":[125,151],"routers,":[126],"prioritizes":[128],"traffic":[131],"by":[132],"allowing":[133],"blocked":[135],"inbound":[136],"packet":[137,212],"to":[138,218],"advance":[139],"occupy":[141],"dedicated":[143],"buffer.":[145],"The":[146],"buffer":[148],"router":[152],"guarantees":[153],"that":[154],"least":[156],"one":[157],"bubble":[158],"exists":[159],"dependency":[162],"chain":[163],"deadlock,":[167],"thereby":[168],"breaking":[169],"dependency.":[172],"To":[173],"ensure":[174],"correctness":[175],"prevent":[177],"formation":[179],"new":[181],"deadlocks":[182],"recovery,":[184],"(VN)":[187],"separation":[188],"rules":[189],"enforced":[191],"throughout":[192],"recovery":[194,207],"process.":[195],"enables":[198],"efficient":[199],"minimal":[203],"degradation":[205],"state.":[208],"Moreover,":[209],"fine-grained":[211],"packing":[213],"implemented":[215],"improve":[219],"bandwidth":[221],"utilization":[222],"small":[224],"packets.":[225],"Compared":[226],"state-of-the-art":[229],"related":[230],"work,":[231],"achieves":[233],"7.30%\u201366.62%":[234],"latency":[235],"reduction":[236],"cost":[239],"0.77%\u20136.98%":[241],"area":[242],"overhead.":[243]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}