{"id":"https://openalex.org/W4410203958","doi":"https://doi.org/10.1109/tvlsi.2025.3560948","title":"An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier","display_name":"An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier","publication_year":2025,"publication_date":"2025-05-08","ids":{"openalex":"https://openalex.org/W4410203958","doi":"https://doi.org/10.1109/tvlsi.2025.3560948"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3560948","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3560948","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082966162","display_name":"Chenghao Zhang","orcid":"https://orcid.org/0000-0001-5802-3625"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chenghao Zhang","raw_affiliation_strings":["School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087052960","display_name":"Maliang Liu","orcid":"https://orcid.org/0000-0003-3181-3277"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Maliang Liu","raw_affiliation_strings":["School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087571877","display_name":"Yuan Chang","orcid":"https://orcid.org/0000-0003-1125-4041"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Chang","raw_affiliation_strings":["School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101871779","display_name":"Yihang Yang","orcid":"https://orcid.org/0009-0007-1002-649X"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yihang Yang","raw_affiliation_strings":["School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061907702","display_name":"Jinhai Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinhai Xiao","raw_affiliation_strings":["School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100402361","display_name":"Yintang Yang","orcid":"https://orcid.org/0000-0001-9745-5404"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yintang Yang","raw_affiliation_strings":["School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016044907","display_name":"Yuanjin Zheng","orcid":"https://orcid.org/0000-0002-5768-367X"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Yuanjin Zheng","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100706888","display_name":"Yong Chen","orcid":"https://orcid.org/0000-0002-2794-1324"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yong Chen","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5082966162"],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09127217,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"33","issue":"10","first_page":"2658","last_page":"2662"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.992900013923645,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.6948832869529724},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6496927738189697},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.6010075807571411},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5703341364860535},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.5118226408958435},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5006325244903564},{"id":"https://openalex.org/keywords/12-bit","display_name":"12-bit","score":0.48690736293792725},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43494242429733276},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18904253840446472},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1809062659740448},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17385071516036987},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10334894061088562},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.10249185562133789},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.06972044706344604}],"concepts":[{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.6948832869529724},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6496927738189697},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.6010075807571411},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5703341364860535},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.5118226408958435},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5006325244903564},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.48690736293792725},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43494242429733276},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18904253840446472},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1809062659740448},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17385071516036987},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10334894061088562},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.10249185562133789},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.06972044706344604},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3560948","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3560948","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8299999833106995}],"awards":[{"id":"https://openalex.org/G4863992923","display_name":null,"funder_award_id":"8091B02042301","funder_id":"https://openalex.org/F4320335787","funder_display_name":"Fundamental Research Funds for the Central Universities"},{"id":"https://openalex.org/G8567058446","display_name":null,"funder_award_id":"2024CY2GJHX34","funder_id":"https://openalex.org/F4320327777","funder_display_name":"Jiangsu Provincial Key Research and Development Program"}],"funders":[{"id":"https://openalex.org/F4320327777","display_name":"Jiangsu Provincial Key Research and Development Program","ror":null},{"id":"https://openalex.org/F4320335787","display_name":"Fundamental Research Funds for the Central Universities","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2526101322","https://openalex.org/W2789056727","https://openalex.org/W3021649129","https://openalex.org/W3048442933","https://openalex.org/W3090442715","https://openalex.org/W3092218596","https://openalex.org/W3112638864","https://openalex.org/W4226311635","https://openalex.org/W4380785701","https://openalex.org/W4389888431","https://openalex.org/W4406387821","https://openalex.org/W4406894761"],"related_works":["https://openalex.org/W2899084033","https://openalex.org/W4327546585","https://openalex.org/W2411923897","https://openalex.org/W4394546135","https://openalex.org/W4285347720","https://openalex.org/W4240289822","https://openalex.org/W2366843358","https://openalex.org/W3143808432","https://openalex.org/W4389935338","https://openalex.org/W2546877268"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,13,22,27,51,60,65,116,126,133],"single-channel":[4],"4-GS/s":[5,98],"8-bit":[6,19],"hybrid-domain":[7],"analog-to-digital":[8],"converter":[9],"(ADC)":[10],"implemented":[11],"in":[12],"28-nm":[14],"CMOS":[15],"process.":[16],"The":[17,102],"proposed":[18,49],"ADC":[20,105],"combines":[21],"3-bit":[23],"voltage-domain":[24],"stage":[25],"with":[26,50,99],"6-bit":[28,100],"time-domain":[29],"(TD)":[30],"backend":[31,92],"to":[32,72],"take":[33],"full":[34],"advantage":[35],"of":[36,54,83,110,129,136],"the":[37,74,79,84,123,140,147],"voltage":[38],"and":[39,78,88,120,146],"time":[40,53,77,81],"domains.":[41],"A":[42,86],"high-speed":[43],"hybrid-loop":[44],"residue":[45],"amplifier":[46],"(RA)":[47],"is":[48,70,93,143,149],"settling":[52,80],"less":[55],"than":[56],"150":[57],"ps,":[58],"while":[59,139],"non-symmetrical":[61],"pipeline":[62],"timing":[63],"utilizing":[64],"25%":[66],"duty":[67],"cycle":[68],"clock":[69],"used":[71],"increase":[73],"TD":[75,91],"quantization":[76],"margin":[82],"RA.":[85],"low-power":[87],"small-area":[89],"gated-ring-oscillator-based":[90],"employed,":[94],"which":[95],"operates":[96],"at":[97,132],"resolution.":[101],"prototype":[103],"hybrid":[104],"occupies":[106],"an":[107],"active":[108],"area":[109],"0.0114":[111],"mm<sup":[112],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[113],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>.":[114],"Under":[115],"1-V":[117],"power":[118,141],"supply":[119],"Nyquist":[121],"input,":[122],"chip":[124],"achieves":[125],"measured":[127],"ENOB":[128],"6.46":[130],"bits":[131],"conversion":[134],"rate":[135],"4":[137],"GS/s,":[138],"consumption":[142],"10.6":[144],"mW":[145],"FoMw":[148],"29.9":[150],"fJ/conversion-step.":[151]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
