{"id":"https://openalex.org/W4409327147","doi":"https://doi.org/10.1109/tvlsi.2025.3556241","title":"Implementing Homomorphic Encryption-Based Logic Locking in System-On-Chip Designs","display_name":"Implementing Homomorphic Encryption-Based Logic Locking in System-On-Chip Designs","publication_year":2025,"publication_date":"2025-04-10","ids":{"openalex":"https://openalex.org/W4409327147","doi":"https://doi.org/10.1109/tvlsi.2025.3556241"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3556241","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3556241","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5093316059","display_name":"Ye Ziyang","orcid":"https://orcid.org/0000-0001-9391-5442"},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ziyang Ye","raw_affiliation_strings":["Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0001-9391-5442","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0002-6644-4224","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3075,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48289231,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"33","issue":"7","first_page":"2049","last_page":"2053"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9887999892234802,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9882000088691711,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/homomorphic-encryption","display_name":"Homomorphic encryption","score":0.8068397045135498},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6614359021186829},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5210798978805542},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.5114311575889587},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4757254421710968},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.26276034116744995},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07943668961524963}],"concepts":[{"id":"https://openalex.org/C158338273","wikidata":"https://www.wikidata.org/wiki/Q2154943","display_name":"Homomorphic encryption","level":3,"score":0.8068397045135498},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6614359021186829},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5210798978805542},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.5114311575889587},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4757254421710968},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.26276034116744995},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07943668961524963}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3556241","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3556241","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1524250393","https://openalex.org/W1953436618","https://openalex.org/W2031533839","https://openalex.org/W2394993236","https://openalex.org/W2400700555","https://openalex.org/W2463363166","https://openalex.org/W2604912388","https://openalex.org/W3011360178","https://openalex.org/W3114561146","https://openalex.org/W4283368085","https://openalex.org/W4360831961","https://openalex.org/W4390357582","https://openalex.org/W4401990209","https://openalex.org/W4402412287","https://openalex.org/W6606067566","https://openalex.org/W6987020231"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W4408218896","https://openalex.org/W2539930818","https://openalex.org/W4406779505","https://openalex.org/W4403623784","https://openalex.org/W4393118461","https://openalex.org/W4390664647","https://openalex.org/W4408501329"],"abstract_inverted_index":{"This":[0],"study":[1],"presents":[2],"a":[3,18],"logic-locking":[4,29],"scheme":[5],"based":[6],"on":[7],"the":[8,39,47,84],"binary":[9],"ring":[10],"learning":[11],"with":[12,35],"error":[13],"(bin-RLWE)":[14],"algorithm,":[15],"implemented":[16,57],"in":[17,46,76,80],"reduced":[19],"instruction":[20],"set":[21],"computer-five":[22],"(RISC-V)":[23],"system-on-chip":[24],"(SoC)":[25],"design.":[26],"Unlike":[27],"traditional":[28],"methods":[30],"that":[31],"require":[32],"providing":[33],"users":[34],"raw":[36],"locking":[37,58],"parameters,":[38],"proposed":[40],"approach":[41],"secures":[42],"critical":[43],"logic":[44],"paths":[45],"privilege":[48],"switching":[49],"process":[50,89],"without":[51],"exposing":[52],"these":[53],"sensitive":[54],"parameters.":[55],"The":[56,87],"module":[59],"itself":[60],"consumes":[61],"3519":[62],"lookup":[63],"tables":[64],"(LUTs)":[65],"and":[66,78,97],"2645":[67],"registers,":[68],"leading":[69],"to":[70,83],"an":[71],"overall":[72],"overhead":[73],"of":[74],"6.0%":[75],"LUTs":[77],"6.9%":[79],"registers":[81],"compared":[82],"baseline":[85],"system.":[86],"unlock":[88],"requires":[90],"about$2.6~\\mu":[91],"$s,":[92],"introducing":[93],"moderate":[94],"performance":[95],"impact":[96],"primarily":[98],"affecting":[99],"system-level":[100],"operations":[101],"while":[102],"preserving":[103],"user-level":[104],"computational":[105],"efficiency.":[106]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}