{"id":"https://openalex.org/W4408305019","doi":"https://doi.org/10.1109/tvlsi.2025.3543851","title":"Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects","display_name":"Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects","publication_year":2025,"publication_date":"2025-03-11","ids":{"openalex":"https://openalex.org/W4408305019","doi":"https://doi.org/10.1109/tvlsi.2025.3543851"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3543851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3543851","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029144871","display_name":"Ya-Rou Hsu","orcid":"https://orcid.org/0000-0002-0213-0162"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ya-Rou Hsu","raw_affiliation_strings":["Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-0213-0162","affiliations":[{"raw_affiliation_string":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045456913","display_name":"Aaron C.-W. Liang","orcid":"https://orcid.org/0000-0002-8237-0878"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Aaron C.-W. Liang","raw_affiliation_strings":["Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0002-8237-0878","affiliations":[{"raw_affiliation_string":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013165434","display_name":"Han-Ya Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Han-Ya Tsai","raw_affiliation_strings":["Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089037497","display_name":"Yen\u2010Ju Su","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen-Ju Su","raw_affiliation_strings":["Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0009-0000-0136-7558","affiliations":[{"raw_affiliation_string":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100682308","display_name":"Charles H.\u2010P. Wen","orcid":"https://orcid.org/0000-0003-4623-9941"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Charles H.-P. Wen","raw_affiliation_strings":["Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":"https://orcid.org/0000-0003-4623-9941","affiliations":[{"raw_affiliation_string":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110777122","display_name":"Hsuan\u2010Ming Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210148979","display_name":"MediaTek (Taiwan)","ror":"https://ror.org/05g9jck81","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210148979"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsuan-Ming Huang","raw_affiliation_strings":["MediaTek Inc., Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MediaTek Inc., Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210148979"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05085028,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"33","issue":"6","first_page":"1789","last_page":"1793"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.8601999878883362,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.8601999878883362,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7494999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10551","display_name":"Scheduling and Optimization Algorithms","score":0.7294999957084656,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ranking","display_name":"Ranking (information retrieval)","score":0.8135138750076294},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5698103308677673},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.49438977241516113},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.46944189071655273},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.44257956743240356},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.37247735261917114},{"id":"https://openalex.org/keywords/information-retrieval","display_name":"Information retrieval","score":0.32403355836868286},{"id":"https://openalex.org/keywords/art","display_name":"Art","score":0.08503353595733643},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08118128776550293},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.07963123917579651},{"id":"https://openalex.org/keywords/visual-arts","display_name":"Visual arts","score":0.06221935153007507}],"concepts":[{"id":"https://openalex.org/C189430467","wikidata":"https://www.wikidata.org/wiki/Q7293293","display_name":"Ranking (information retrieval)","level":2,"score":0.8135138750076294},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5698103308677673},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.49438977241516113},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.46944189071655273},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.44257956743240356},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.37247735261917114},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.32403355836868286},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.08503353595733643},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08118128776550293},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.07963123917579651},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.06221935153007507}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3543851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3543851","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1601215252","https://openalex.org/W2007563768","https://openalex.org/W2059001985","https://openalex.org/W2108862644","https://openalex.org/W2142537246","https://openalex.org/W2143331230","https://openalex.org/W2997716136","https://openalex.org/W3100453629","https://openalex.org/W3211857759","https://openalex.org/W4225287629","https://openalex.org/W4225335175","https://openalex.org/W4285169970","https://openalex.org/W4353031993","https://openalex.org/W4387146044","https://openalex.org/W4392680688","https://openalex.org/W6632992187","https://openalex.org/W6681009388"],"related_works":["https://openalex.org/W2118564381","https://openalex.org/W2163901716","https://openalex.org/W2152204162","https://openalex.org/W2739821120","https://openalex.org/W2088097596","https://openalex.org/W2150136235","https://openalex.org/W2140661912","https://openalex.org/W2037724912","https://openalex.org/W2056806613","https://openalex.org/W2153069032"],"abstract_inverted_index":{"Cell":[0],"layout":[1,12,84,124],"generation":[2],"plays":[3],"a":[4,73,139,151],"crucial":[5],"role":[6],"in":[7,25,94,133,138],"design":[8,18],"automation.":[9],"The":[10,114],"generated":[11],"must":[13],"not":[14],"only":[15,106],"adhere":[16],"to":[17,45,78],"rules":[19],"but":[20],"also":[21],"exhibit":[22],"optimized":[23],"performance":[24,55,81],"terms":[26],"of":[27,86,101],"factors":[28],"such":[29],"as":[30],"delay,":[31],"power,":[32],"area,":[33],"and":[34,104],"cost.":[35],"However,":[36],"prior":[37],"works":[38],"often":[39],"rely":[40],"on":[41],"metrics":[42],"that":[43,117],"fail":[44],"consider":[46],"the":[47,53,107,122,161],"layout-dependent":[48],"effects":[49],"(LDEs).":[50],"Furthermore,":[51],"evaluating":[52,105],"actual":[54],"using":[56],"commercial":[57],"tools":[58],"can":[59],"be":[60],"excessively":[61],"time-consuming,":[62],"especially":[63],"when":[64],"iteratively":[65],"optimizing":[66],"cell":[67,102,148],"layouts.":[68],"Therefore,":[69],"this":[70,118],"work":[71],"proposes":[72],"new":[74],"machine-learning(ML)-based":[75],"ranking":[76,82],"model":[77,90],"enable":[79],"rapid":[80],"between":[83],"candidates":[85,111],"standard":[87,147],"cells.":[88],"This":[89],"incorporates":[91],"all":[92],"LDEs":[93],"feature":[95],"extraction,":[96],"generating":[97],"an":[98],"ordered":[99],"list":[100],"layouts,":[103],"top-<italic":[108],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[109,153],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">K</i>":[110],"for":[112],"performance.":[113],"experiments":[115],"show":[116],"approach":[119],"successfully":[120],"identifies":[121],"optimal":[123],"from":[125],"ten":[126],"benchmark":[127],"cells,":[128],"which":[129],"are":[130],"most":[131],"used":[132],"intellectual":[134],"property":[135],"(IP)":[136],"cores,":[137],"sub-5":[140],"nm":[141],"fin":[142],"field-effect":[143],"transistor":[144],"(FinFET)":[145],"industrial":[146],"library,":[149],"achieving":[150],"<inline-formula":[152],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[154],"<tex-math":[155],"notation=\"LaTeX\">$348\\times":[156],"$":[157],"</tex-math></inline-formula>":[158],"speedup":[159],"over":[160],"conventional":[162],"flow.":[163]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
