{"id":"https://openalex.org/W4406727833","doi":"https://doi.org/10.1109/tvlsi.2025.3528320","title":"Protecting Analog Circuits Using Switch Mode Time Domain Locking","display_name":"Protecting Analog Circuits Using Switch Mode Time Domain Locking","publication_year":2025,"publication_date":"2025-01-22","ids":{"openalex":"https://openalex.org/W4406727833","doi":"https://doi.org/10.1109/tvlsi.2025.3528320"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2025.3528320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3528320","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115995017","display_name":"Utkarsh Kumar","orcid":"https://orcid.org/0009-0001-8795-2754"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Utkarsh Kumar","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA"],"raw_orcid":"https://orcid.org/0009-0001-8795-2754","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109252424","display_name":"Sudhanshu Khanna","orcid":null},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhanshu Khanna","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051965447","display_name":"Ankit Mittal","orcid":"https://orcid.org/0000-0001-8761-2269"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ankit Mittal","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA"],"raw_orcid":"https://orcid.org/0000-0001-8761-2269","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020694155","display_name":"Aatmesh Shrivastava","orcid":"https://orcid.org/0000-0002-5738-9868"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aatmesh Shrivastava","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA"],"raw_orcid":"https://orcid.org/0000-0002-5738-9868","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5115995017"],"corresponding_institution_ids":["https://openalex.org/I12912129"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00852254,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"33","issue":"4","first_page":"916","last_page":"928"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.991100013256073,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44488292932510376},{"id":"https://openalex.org/keywords/time-domain","display_name":"Time domain","score":0.4114189147949219}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44488292932510376},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.4114189147949219},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2025.3528320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2025.3528320","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6399999856948853,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G1415086044","display_name":null,"funder_award_id":"CCSS-2144703","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G3043258596","display_name":null,"funder_award_id":"CCSS-2125222","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G3286993448","display_name":null,"funder_award_id":"IUCRC P24_2024","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G4110894167","display_name":null,"funder_award_id":"CHEST IUCRC P24_2024","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5404076434","display_name":null,"funder_award_id":"CCSS-2225368","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":50,"referenced_works":["https://openalex.org/W1524250393","https://openalex.org/W1973175885","https://openalex.org/W1982288276","https://openalex.org/W1992889283","https://openalex.org/W1999162711","https://openalex.org/W2063615695","https://openalex.org/W2093439000","https://openalex.org/W2099101940","https://openalex.org/W2103509612","https://openalex.org/W2109083654","https://openalex.org/W2112611349","https://openalex.org/W2123482651","https://openalex.org/W2129004891","https://openalex.org/W2139801901","https://openalex.org/W2152333361","https://openalex.org/W2154909745","https://openalex.org/W2295460135","https://openalex.org/W2300090351","https://openalex.org/W2343475170","https://openalex.org/W2419784917","https://openalex.org/W2468843375","https://openalex.org/W2510156037","https://openalex.org/W2511192821","https://openalex.org/W2609004879","https://openalex.org/W2625363942","https://openalex.org/W2747980214","https://openalex.org/W2782164439","https://openalex.org/W2910838140","https://openalex.org/W2943129030","https://openalex.org/W2960724128","https://openalex.org/W3045422389","https://openalex.org/W3046266258","https://openalex.org/W3083004312","https://openalex.org/W3088175788","https://openalex.org/W3088779417","https://openalex.org/W3095491424","https://openalex.org/W3099336459","https://openalex.org/W3118075076","https://openalex.org/W3185792152","https://openalex.org/W3201826149","https://openalex.org/W3209974339","https://openalex.org/W3215550323","https://openalex.org/W4210621891","https://openalex.org/W4232836212","https://openalex.org/W4234937017","https://openalex.org/W4285255616","https://openalex.org/W4308219400","https://openalex.org/W4385300775","https://openalex.org/W4392746425","https://openalex.org/W4396214985"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W4391913857","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052"],"abstract_inverted_index":{"Analog":[0],"circuits":[1,54,103],"remain":[2],"vulnerable":[3],"to":[4,30,97,137],"different":[5],"types":[6],"of":[7,44,56,85,100,166],"supply":[8],"chain":[9],"attacks":[10],"including":[11],"piracy,":[12],"overproduction,":[13],"counterfeiting,":[14],"and":[15,121],"reverse":[16],"engineering.":[17],"In":[18,129],"this":[19,113],"article,":[20],"we":[21,132],"present":[22],"switch":[23],"mode":[24],"time":[25],"domain":[26],"locking":[27,38,92],"(SMDL)":[28],"technique":[29,35,93,114],"protect":[31],"analog":[32,53,102],"circuits.":[33],"This":[34],"integrates":[36],"a":[37,70,98,116,123,134,147],"mechanism":[39],"into":[40],"the":[41,45,139,160],"time-domain":[42],"functionality":[43],"circuit.":[46,128],"It":[47],"uses":[48],"random-key-based":[49],"switching":[50,65],"phases":[51,66,86],"for":[52],"instead":[55],"fixed":[57],"clocks":[58],"that":[59],"are":[60,67],"conventionally":[61],"used.":[62],"The":[63,91,142],"random":[64],"dependent":[68],"on":[69,115,122],"key":[71,80,136,153],"which":[72],"can":[73,87,94],"be":[74,95],"made":[75],"arbitrarily":[76],"long.":[77],"A":[78],"correct":[79,83],"(CK)":[81],"with":[82],"alignment":[84],"unlock":[88],"circuit":[89,140,161],"functionality.":[90,141],"applied":[96],"variety":[99],"switch-mode":[101],"such":[104],"as":[105],"filters,":[106],"amplifiers,":[107],"regulators,":[108],"among":[109],"others.":[110],"We":[111],"implemented":[112,145],"folded":[117],"cascode":[118],"amplifier":[119],"(FCA)":[120],"switched-capacitor":[124],"bandgap":[125],"reference":[126],"(BGR)":[127],"both":[130],"techniques,":[131],"employ":[133],"128-bit":[135],"lock":[138],"design":[143],"is":[144],"in":[146,159],"65-nm":[148],"CMOS":[149],"technology.":[150],"An":[151],"incorrect":[152],"(IK)":[154],"introduces":[155],"almost":[156],"100%":[157],"variation":[158],"functionality,":[162],"ensuring":[163],"high":[164],"level":[165],"security.":[167]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
