{"id":"https://openalex.org/W4405800355","doi":"https://doi.org/10.1109/tvlsi.2024.3510697","title":"ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling","display_name":"ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling","publication_year":2024,"publication_date":"2024-12-25","ids":{"openalex":"https://openalex.org/W4405800355","doi":"https://doi.org/10.1109/tvlsi.2024.3510697"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2024.3510697","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3510697","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048354111","display_name":"Chenghong Zhang","orcid":"https://orcid.org/0009-0000-5656-3142"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chenghong Zhang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073803879","display_name":"Dongliang Xiong","orcid":"https://orcid.org/0000-0002-4882-7504"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dongliang Xiong","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100372789","display_name":"Xiaoxu Zhang","orcid":"https://orcid.org/0009-0003-0130-0793"},"institutions":[{"id":"https://openalex.org/I75059550","display_name":"Zhejiang Gongshang University","ror":"https://ror.org/0569mkk41","country_code":"CN","type":"education","lineage":["https://openalex.org/I75059550"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoxu Zhang","raw_affiliation_strings":["School of Information and Electronic Engineering, Zhejiang Gongshang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"School of Information and Electronic Engineering, Zhejiang Gongshang University, Hangzhou, China","institution_ids":["https://openalex.org/I75059550"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053965487","display_name":"Zikang Wang","orcid":"https://orcid.org/0000-0003-4995-5521"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhengyu Wang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047419048","display_name":"Huotao Gao","orcid":"https://orcid.org/0000-0001-7048-6411"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huibo Gao","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032185713","display_name":"Kai Huang","orcid":"https://orcid.org/0000-0002-5034-7171"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Kai Huang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5048354111"],"corresponding_institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.2225,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.5673145,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"33","issue":"5","first_page":"1396","last_page":"1406"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9779000282287598,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9685999751091003,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7199330925941467},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.6793384552001953},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6047531962394714},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.5963963866233826},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4138909876346588},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3244897723197937},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20429012179374695},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14754390716552734},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1133461594581604},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09312811493873596}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7199330925941467},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.6793384552001953},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6047531962394714},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5963963866233826},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4138909876346588},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3244897723197937},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20429012179374695},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14754390716552734},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1133461594581604},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09312811493873596},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2024.3510697","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3510697","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G3668600660","display_name":null,"funder_award_id":"226-2024-00154","funder_id":"https://openalex.org/F4320335787","funder_display_name":"Fundamental Research Funds for the Central Universities"}],"funders":[{"id":"https://openalex.org/F4320335787","display_name":"Fundamental Research Funds for the Central Universities","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1546526482","https://openalex.org/W1996183863","https://openalex.org/W2071429830","https://openalex.org/W2082557039","https://openalex.org/W2086032532","https://openalex.org/W2099279767","https://openalex.org/W2141565132","https://openalex.org/W2519730952","https://openalex.org/W2743713949","https://openalex.org/W2761878354","https://openalex.org/W2763006490","https://openalex.org/W2796387454","https://openalex.org/W2933263187","https://openalex.org/W2944830921","https://openalex.org/W2963443127","https://openalex.org/W2986931132","https://openalex.org/W2990042152","https://openalex.org/W3048958644","https://openalex.org/W3087771103","https://openalex.org/W3114989627","https://openalex.org/W3124821958","https://openalex.org/W4313026382","https://openalex.org/W4382119953","https://openalex.org/W4386025587","https://openalex.org/W4386065195","https://openalex.org/W4390604590","https://openalex.org/W4390970417"],"related_works":["https://openalex.org/W2116677773","https://openalex.org/W1967088250","https://openalex.org/W2155261584","https://openalex.org/W2584231425","https://openalex.org/W2150611273","https://openalex.org/W4207086172","https://openalex.org/W2042919702","https://openalex.org/W2054730497","https://openalex.org/W4225981436","https://openalex.org/W2156185805"],"abstract_inverted_index":{"Timing":[0],"error":[1,23,55,64],"prediction":[2,24,56,65],"circuits":[3,25],"have":[4,26],"demonstrated":[5],"greater":[6],"efficiency":[7],"in":[8,43,47,77,203],"reducing":[9,93],"the":[10,28,78,83,98,115,120,141,145,166],"worst":[11],"case":[12],"timing":[13,22,54,63],"margins":[14],"of":[15,21,36,89,117,122,147],"conventional":[16],"circuits.":[17],"However,":[18],"prior":[19],"works":[20],"complicated":[27],"clock":[29,90,99],"tree":[30],"or":[31,119],"introduced":[32],"a":[33,44,154,187,193,200],"substantial":[34],"number":[35],"delay":[37,75],"cells":[38],"along":[39],"data":[40],"paths,":[41],"resulting":[42],"considerable":[45],"increase":[46],"area":[48,94,195],"overhead.":[49],"This":[50,136],"work":[51],"introduces":[52],"asynchronous":[53,69],"circuit":[57,73,175],"(ATEP),":[58],"an":[59,105,177],"ATEP":[60],"that":[61],"integrates":[62],"technology":[66],"with":[67,191],"bundle-data":[68],"templates.":[70],"The":[71],"proposed":[72],"leverages":[74],"lines":[76],"request":[79],"wire":[80],"to":[81,130,133,139,144,160,186,199],"generate":[82],"warning":[84,123,156,162],"detection":[85],"window":[86],"(WDW)":[87],"independent":[88],"signals,":[91],"thereby":[92],"overhead":[95],"and":[96,108,197],"streamlining":[97],"tree.":[100],"In":[101],"addition,":[102],"we":[103,152],"present":[104],"adaptive":[106],"voltage":[107],"frequency":[109,142],"scaling":[110],"(AVFS)":[111],"controller,":[112],"which":[113],"evaluates":[114],"likelihood":[116],"warnings":[118],"quantity":[121],"paths":[124],"based":[125,164],"on":[126,165,176],"path":[127],"activation":[128],"rates":[129],"determine":[131],"when":[132],"cease":[134],"adjustments.":[135],"strategy":[137,159],"helps":[138],"identify":[140],"closer":[143],"point":[146],"first":[148],"failure":[149],"(PoFF).":[150],"Furthermore,":[151],"propose":[153],"dynamic":[155],"detector":[157],"gating":[158],"gate":[161],"detectors":[163],"current":[167],"environment,":[168],"further":[169],"decreasing":[170],"power":[171,204],"consumption.":[172,205],"Implementing":[173],"this":[174],"RISC-V":[178],"processor,":[179],"targeting":[180],"28-nm":[181],"CMOS":[182],"technology,":[183],"yields":[184],"up":[185,198],"56.8%":[188],"performance":[189],"improvement":[190],"only":[192],"3.79%":[194],"cost":[196],"28.0%":[201],"reduction":[202]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-02-25T08:12:03.925757","created_date":"2025-10-10T00:00:00"}