{"id":"https://openalex.org/W4405269803","doi":"https://doi.org/10.1109/tvlsi.2024.3509439","title":"A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications","display_name":"A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications","publication_year":2024,"publication_date":"2024-12-11","ids":{"openalex":"https://openalex.org/W4405269803","doi":"https://doi.org/10.1109/tvlsi.2024.3509439"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2024.3509439","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3509439","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5115394902","display_name":"Chenxi Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chenxi Chen","raw_affiliation_strings":["Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China"],"raw_orcid":"https://orcid.org/0009-0008-8245-989X","affiliations":[{"raw_affiliation_string":"Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]},{"raw_affiliation_string":"State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jinhong Wang","orcid":"https://orcid.org/0000-0002-9588-0076"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinhong Wang","raw_affiliation_strings":["Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China"],"raw_orcid":"https://orcid.org/0000-0002-9588-0076","affiliations":[{"raw_affiliation_string":"Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]},{"raw_affiliation_string":"State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103492114","display_name":"Xueye Hu","orcid":null},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xueye Hu","raw_affiliation_strings":["Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]},{"raw_affiliation_string":"State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"last","author":{"id":null,"display_name":"Shubin Liu","orcid":"https://orcid.org/0000-0002-4969-9508"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China"],"raw_orcid":"https://orcid.org/0000-0002-4969-9508","affiliations":[{"raw_affiliation_string":"Department of Modern Physics, State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]},{"raw_affiliation_string":"State Key Laboratory of Particle Detection and Electronics and the Department of Modern Physics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I126520041"],"apc_list":null,"apc_paid":null,"fwci":0.159,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.48060425,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"33","issue":"5","first_page":"1384","last_page":"1395"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9765999913215637,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9765999913215637,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9739999771118164,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9542999863624573,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6469798684120178},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.6411430835723877},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5525739192962646},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5089707374572754},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4994473457336426},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39996978640556335},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26243001222610474},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23763760924339294},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2191835641860962}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6469798684120178},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6411430835723877},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5525739192962646},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5089707374572754},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4994473457336426},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39996978640556335},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26243001222610474},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23763760924339294},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2191835641860962}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2024.3509439","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3509439","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8199999928474426,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G2707282466","display_name":null,"funder_award_id":"12025504","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1643721902","https://openalex.org/W1855253372","https://openalex.org/W1895576399","https://openalex.org/W1973127083","https://openalex.org/W2129182275","https://openalex.org/W2130869059","https://openalex.org/W2140489157","https://openalex.org/W2145469556","https://openalex.org/W2147539712","https://openalex.org/W2156435621","https://openalex.org/W2173501456","https://openalex.org/W2513702809","https://openalex.org/W2533128568","https://openalex.org/W2592023703","https://openalex.org/W2615189621","https://openalex.org/W2761003783","https://openalex.org/W2794898833","https://openalex.org/W2884598006","https://openalex.org/W2887124275","https://openalex.org/W2945378913","https://openalex.org/W2973780393","https://openalex.org/W2987827054","https://openalex.org/W3093685770","https://openalex.org/W3134198949","https://openalex.org/W4200246836","https://openalex.org/W4237720872","https://openalex.org/W4242164861","https://openalex.org/W4290648676","https://openalex.org/W4386212296"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2316202402","https://openalex.org/W2074043759","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841"],"abstract_inverted_index":{"In":[0],"recent":[1],"years,":[2],"field-programmable":[3],"gate":[4],"arrays":[5],"(FPGAs)":[6],"have":[7],"become":[8],"critical":[9],"computing":[10],"resources,":[11],"featuring":[12,87],"higher":[13],"levels":[14],"of":[15,63,103,105,126,139,153],"system":[16],"integration":[17],"and":[18,30,36,48,80,91,109,136,148,166,182,188],"accelerated":[19],"clocking":[20],"speeds.":[21],"FPGA-based":[22],"systems":[23],"face":[24],"increasing":[25],"challenges":[26],"in":[27,96,113,116],"maintaining":[28],"power":[29,38,54,64],"signal":[31,66],"integrity.":[32,67],"Consequently,":[33],"a":[34,71,75,81,123,137,170],"flexible":[35],"efficient":[37],"supply":[39,65],"monitor":[40,69,79,108,155,160],"is":[41,156,167],"essential":[42],"for":[43],"evaluating":[44],"the":[45,101,106,149,154],"system\u2019s":[46],"performance":[47],"reliability.":[49],"We":[50,99],"propose":[51],"an":[52,58,117],"integrated":[53],"monitoring":[55],"scheme":[56],"within":[57],"FPGA,":[59,120],"enabling":[60],"real-time":[61],"evaluation":[62],"The":[68,159],"employs":[70],"hybrid":[72,107],"structure":[73],"combining":[74],"ring":[76],"oscillator":[77],"(RO)-based":[78],"tapped":[82],"delay":[83],"line":[84],"(TDL)-based":[85],"monitor,":[86],"first-order":[88],"noise":[89],"shaping":[90],"explicit":[92],"dynamic-element":[93],"matching":[94],"(DEM)":[95],"its":[97,111],"quantization.":[98],"analyze":[100],"principle":[102],"operation":[104],"present":[110],"implementation":[112],"FPGAs.":[114],"Demonstrated":[115],"AMD":[118],"Kintex-7":[119],"tests":[121],"show":[122],"voltage":[124],"resolution":[125],"at":[127],"least":[128],"<inline-formula":[129],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[130,141],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[131,142],"<tex-math":[132,143],"notation=\"LaTeX\">$12.96~\\mu":[133],"$":[134,145],"</tex-math></inline-formula>V":[135,146],"precision":[138],"8.03-<inline-formula":[140],"notation=\"LaTeX\">$\\mu":[144],"rms,":[147],"effective":[150],"bandwidth":[151],"(BW)":[152],"10":[157],"MHz.":[158],"utilizes":[161],"only":[162],"conventional":[163],"logic":[164,172],"resources":[165],"delivered":[168],"as":[169],"soft":[171],"core.":[173],"It":[174],"can":[175],"be":[176],"migrated":[177],"to":[178],"different":[179],"FPGA":[180],"platforms":[181],"custom-integrated":[183],"circuits":[184],"with":[185],"greater":[186],"flexibility":[187],"integration.":[189]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}