{"id":"https://openalex.org/W4405021899","doi":"https://doi.org/10.1109/tvlsi.2024.3504539","title":"An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory","display_name":"An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory","publication_year":2024,"publication_date":"2024-12-04","ids":{"openalex":"https://openalex.org/W4405021899","doi":"https://doi.org/10.1109/tvlsi.2024.3504539"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2024.3504539","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3504539","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100782289","display_name":"Hayoung Lee","orcid":"https://orcid.org/0000-0002-6868-0829"},"institutions":[{"id":"https://openalex.org/I57664883","display_name":"Ajou University","ror":"https://ror.org/03tzb2h73","country_code":"KR","type":"education","lineage":["https://openalex.org/I57664883"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hayoung Lee","raw_affiliation_strings":["Department of Intelligence Semiconductor Engineering, Ajou University, Suwon, South Korea"],"raw_orcid":"https://orcid.org/0000-0002-6868-0829","affiliations":[{"raw_affiliation_string":"Department of Intelligence Semiconductor Engineering, Ajou University, Suwon, South Korea","institution_ids":["https://openalex.org/I57664883"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Juyong Lee","orcid":"https://orcid.org/0009-0006-0102-3695"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Juyong Lee","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0009-0006-0102-3695","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":null,"display_name":"Sungho Kang","orcid":"https://orcid.org/0000-0002-7093-2095"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungho Kang","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"],"raw_orcid":"https://orcid.org/0000-0002-7093-2095","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8558,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.87038579,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"33","issue":"5","first_page":"1452","last_page":"1456"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.6615215539932251},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.563910186290741},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5639097094535828},{"id":"https://openalex.org/keywords/memory-test","display_name":"Memory test","score":0.4657949209213257},{"id":"https://openalex.org/keywords/test-method","display_name":"Test method","score":0.4566650986671448},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4416581988334656},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3609665036201477},{"id":"https://openalex.org/keywords/psychology","display_name":"Psychology","score":0.1320262849330902},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06747642159461975}],"concepts":[{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.6615215539932251},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.563910186290741},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5639097094535828},{"id":"https://openalex.org/C3017990537","wikidata":"https://www.wikidata.org/wiki/Q6815759","display_name":"Memory test","level":3,"score":0.4657949209213257},{"id":"https://openalex.org/C132519959","wikidata":"https://www.wikidata.org/wiki/Q3077373","display_name":"Test method","level":2,"score":0.4566650986671448},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4416581988334656},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3609665036201477},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.1320262849330902},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06747642159461975},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C169900460","wikidata":"https://www.wikidata.org/wiki/Q2200417","display_name":"Cognition","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C169760540","wikidata":"https://www.wikidata.org/wiki/Q207011","display_name":"Neuroscience","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2024.3504539","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3504539","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.41999998688697815,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G6321057740","display_name":null,"funder_award_id":"2022R1A2B5B03002504","funder_id":"https://openalex.org/F4320322120","funder_display_name":"National Research Foundation of Korea"}],"funders":[{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2605347906","https://openalex.org/W2613989746","https://openalex.org/W2944349874","https://openalex.org/W3040646053","https://openalex.org/W3100710793","https://openalex.org/W3131039502","https://openalex.org/W3189166979","https://openalex.org/W4226126604","https://openalex.org/W4239722617","https://openalex.org/W4295036115","https://openalex.org/W4297097348"],"related_works":["https://openalex.org/W2588198209","https://openalex.org/W1909006023","https://openalex.org/W4205824991","https://openalex.org/W3200723557","https://openalex.org/W4312713546","https://openalex.org/W2362195430","https://openalex.org/W2347494122","https://openalex.org/W2567983276","https://openalex.org/W2802298219","https://openalex.org/W2038503502"],"abstract_inverted_index":{"With":[0],"the":[1,8,80,95,115,123,135],"rapid":[2],"advances":[3],"in":[4,51,105,139],"artificial":[5],"intelligence":[6],"(AI),":[7],"demand":[9],"for":[10,75,130],"data-intensive":[11],"analytics":[12],"has":[13,21,30],"surged.":[14],"Consequently,":[15],"extensive":[16],"research":[17],"on":[18],"AI":[19,26,35],"acceleration":[20,36],"been":[22],"conducted":[23],"to":[24,55,87],"enhance":[25],"performance.":[27],"Processing-in-memory":[28],"(PiM)":[29],"emerged":[31],"as":[32],"a":[33,70,110,140],"promising":[34],"architecture,":[37],"offering":[38],"an":[39,64],"unprecedented":[40],"high-bandwidth":[41],"connection":[42],"between":[43],"compute":[44],"and":[45,82],"memory.":[46],"However,":[47],"integrating":[48],"many":[49],"components":[50],"PiM":[52,86,131],"can":[53,91,127],"lead":[54],"yield":[56],"degradation.":[57],"To":[58],"address":[59],"this":[60],"issue,":[61],"we":[62],"propose":[63],"efficient":[65],"test":[66,112,119],"architecture":[67,78],"that":[68],"utilizes":[69,79],"hybrid":[71],"built-in":[72],"self-test":[73,126],"(BIST)":[74],"PiM.":[76,106],"This":[77],"structural":[81],"operational":[83],"characteristics":[84],"of":[85,118,125,134],"facilitate":[88],"testing.":[89],"It":[90],"execute":[92],"testing":[93],"through":[94,132],"existing":[96,136],"functional":[97],"paths":[98],"without":[99],"requiring":[100],"any":[101],"additional":[102],"hardware":[103],"implementation":[104],"Furthermore,":[107],"it":[108],"achieves":[109],"100%":[111],"coverage":[113],"with":[114],"small":[116,142],"number":[117],"patterns.":[120],"In":[121],"addition,":[122],"functionality":[124],"be":[128],"realized":[129],"reconfiguration":[133],"hardware,":[137],"resulting":[138],"very":[141],"area":[143],"overhead.":[144]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":4}],"updated_date":"2026-08-12T21:12:35.861297","created_date":"2025-10-10T00:00:00"}
