{"id":"https://openalex.org/W4404627651","doi":"https://doi.org/10.1109/tvlsi.2024.3496931","title":"A 7.4\u20139.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration","display_name":"A 7.4\u20139.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration","publication_year":2024,"publication_date":"2024-11-22","ids":{"openalex":"https://openalex.org/W4404627651","doi":"https://doi.org/10.1109/tvlsi.2024.3496931"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2024.3496931","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3496931","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051442708","display_name":"Feng Bu","orcid":"https://orcid.org/0000-0003-3761-6848"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Feng Bu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029968632","display_name":"Ruixue Ding","orcid":"https://orcid.org/0000-0001-9296-535X"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruixue Ding","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0001-9296-535X","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087274166","display_name":"Depeng Sun","orcid":"https://orcid.org/0009-0002-2646-0235"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Depeng Sun","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0009-0002-2646-0235","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100400458","display_name":"Ge Wang","orcid":"https://orcid.org/0000-0002-2656-7705"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ge Wang","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100592911","display_name":"Yuan Gao","orcid":"https://orcid.org/0009-0008-0606-1097"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Gao","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101800335","display_name":"Rong Zhou","orcid":"https://orcid.org/0000-0002-0966-3711"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rong Zhou","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-0966-3711","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003457423","display_name":"Xiaoteng Zhao","orcid":"https://orcid.org/0000-0002-9447-8763"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoteng Zhao","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-9447-8763","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032827654","display_name":"Lisheng Chen","orcid":"https://orcid.org/0000-0002-1354-2824"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lisheng Chen","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-1354-2824","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Shubin Liu","orcid":"https://orcid.org/0000-0002-9942-0069"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-9942-0069","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":null,"display_name":"Zhangming Zhu","orcid":"https://orcid.org/0000-0002-7764-1928"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhangming Zhu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-7764-1928","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Integrated Circuits, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]},{"raw_affiliation_string":"School of Integrated Circuits, Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5051442708"],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":0.3762,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61846174,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"33","issue":"5","first_page":"1442","last_page":"1446"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11160","display_name":"Acoustic Wave Resonator Technologies","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7875359058380127},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.6825923323631287},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.6129682660102844},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.5865480303764343},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5344995856285095},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.5159392952919006},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.4492199122905731},{"id":"https://openalex.org/keywords/time-domain","display_name":"Time domain","score":0.4176478981971741},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.37417927384376526},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34965330362319946},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.26186737418174744},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22614294290542603},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.21537700295448303},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21469110250473022},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17779889702796936},{"id":"https://openalex.org/keywords/mathematical-analysis","display_name":"Mathematical analysis","score":0.1464114785194397},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.08411690592765808},{"id":"https://openalex.org/keywords/thermodynamics","display_name":"Thermodynamics","score":0.05856943130493164}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7875359058380127},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.6825923323631287},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.6129682660102844},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.5865480303764343},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5344995856285095},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.5159392952919006},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.4492199122905731},{"id":"https://openalex.org/C103824480","wikidata":"https://www.wikidata.org/wiki/Q185889","display_name":"Time domain","level":2,"score":0.4176478981971741},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.37417927384376526},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34965330362319946},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.26186737418174744},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22614294290542603},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.21537700295448303},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21469110250473022},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17779889702796936},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.1464114785194397},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.08411690592765808},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.05856943130493164},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2024.3496931","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3496931","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7799999713897705,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G1029855781","display_name":null,"funder_award_id":"JB191113","funder_id":"https://openalex.org/F4320335787","funder_display_name":"Fundamental Research Funds for the Central Universities"},{"id":"https://openalex.org/G1079207299","display_name":null,"funder_award_id":"62090044","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2320218852","display_name":null,"funder_award_id":"62021004","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2344047301","display_name":null,"funder_award_id":"2022YFB4401200","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G2351528596","display_name":null,"funder_award_id":"62227816","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G3438427983","display_name":null,"funder_award_id":"62304168","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4552170216","display_name":null,"funder_award_id":"62161160309","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4765864460","display_name":null,"funder_award_id":"62261160649","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null},{"id":"https://openalex.org/F4320335787","display_name":"Fundamental Research Funds for the Central Universities","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W2180378519","https://openalex.org/W2342426112","https://openalex.org/W3018467755","https://openalex.org/W3186283937","https://openalex.org/W3201131231","https://openalex.org/W3205565959","https://openalex.org/W4213130883","https://openalex.org/W4220717521","https://openalex.org/W4226300369","https://openalex.org/W4285272142","https://openalex.org/W4293812021","https://openalex.org/W4293812167","https://openalex.org/W4312261872","https://openalex.org/W4376150531","https://openalex.org/W4387490577","https://openalex.org/W4391892585"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2097523295","https://openalex.org/W4360861688","https://openalex.org/W3134930219","https://openalex.org/W2967785526","https://openalex.org/W2908000842","https://openalex.org/W2065391525","https://openalex.org/W2113001378","https://openalex.org/W4318711045","https://openalex.org/W1993045784"],"abstract_inverted_index":{"This":[0],"brief":[1],"proposes":[2],"a":[3,52,124,128],"7.4\u20139.2-GHz":[4],"low-noise":[5],"fractional-N":[6,99],"differential":[7,65],"sampling":[8,46,66],"phase-locked":[9],"loop":[10],"(DSPLL),":[11],"which":[12,69],"features":[13],"doubled":[14],"phase":[15],"detector":[16],"(PD)":[17],"gain.":[18],"By":[19],"using":[20],"the":[21,27,33,40,60,72,84,109],"phase-domain":[22],"and":[23,39,93,98,108],"voltage-domain":[24],"hybrid":[25],"calibration,":[26],"accumulated":[28],"quantization":[29],"error":[30],"(Q-error)":[31],"of":[32,64,74,91,130,134],"delta-sigma":[34],"modulator":[35],"(DSM)":[36],"is":[37,49,56,105,113,120],"compensated,":[38],"locking":[41],"problem":[42],"caused":[43],"by":[44],"large":[45],"voltage":[47,53,62],"fluctuation":[48],"solved.":[50],"Meanwhile,":[51],"shifting":[54],"technique":[55],"introduced":[57],"to":[58],"adjust":[59],"locked":[61],"region":[63],"PD":[67],"(DSPD),":[68],"can":[70],"improve":[71],"linearity":[73],"DSPLL":[75,86],"for":[76,96],"better":[77],"calibration.":[78],"Fabricated":[79],"in":[80],"65-nm":[81],"CMOS":[82],"process,":[83],"presented":[85],"achieves":[87],"measured":[88],"integrated":[89],"jitter":[90,132],"69.09":[92],"73.26":[94],"fs":[95],"integer-N":[97],"modes,":[100],"respectively.":[101],"The":[102,116],"reference":[103],"spur":[104,112],"\u221272.96":[106],"dBc,":[107],"worst":[110],"fractional":[111],"\u221255.26":[114],"dBc.":[115],"total":[117],"power":[118],"consumption":[119],"19.2":[121],"mW":[122],"at":[123],"1.2-V":[125],"supply,":[126],"achieving":[127],"figure":[129],"merit":[131],"(FOMJ)":[133],"\u2212249.9":[135],"dB.":[136]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-03T09:05:47.796612","created_date":"2025-10-10T00:00:00"}
