{"id":"https://openalex.org/W4403277416","doi":"https://doi.org/10.1109/tvlsi.2024.3465010","title":"A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering","display_name":"A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering","publication_year":2024,"publication_date":"2024-10-09","ids":{"openalex":"https://openalex.org/W4403277416","doi":"https://doi.org/10.1109/tvlsi.2024.3465010"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2024.3465010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3465010","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101892407","display_name":"Zihang Wang","orcid":"https://orcid.org/0009-0007-1273-3112"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zihang Wang","raw_affiliation_strings":["School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109520030","display_name":"Yushu Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yushu Yang","raw_affiliation_strings":["School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jianfei Wang","orcid":"https://orcid.org/0009-0004-0132-3319"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianfei Wang","raw_affiliation_strings":["School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China"],"raw_orcid":"https://orcid.org/0009-0004-0132-3319","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042282822","display_name":"Jia Hou","orcid":"https://orcid.org/0009-0007-1744-3667"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jia Hou","raw_affiliation_strings":["School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100728012","display_name":"Yang Su","orcid":"https://orcid.org/0000-0003-3619-7936"},"institutions":[{"id":"https://openalex.org/I4210134428","display_name":"Chinese People's Armed Police Force Engineering University","ror":"https://ror.org/031jzbb03","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210134428"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yang Su","raw_affiliation_strings":["School of Cryptography Engineering, Engineering University of People&#x2019;s Armed Police, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0003-3619-7936","affiliations":[{"raw_affiliation_string":"School of Cryptography Engineering, Engineering University of People&#x2019;s Armed Police, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I4210134428"]}]},{"author_position":"last","author":{"id":null,"display_name":"Chen Yang","orcid":"https://orcid.org/0000-0002-8221-7670"},"institutions":[{"id":"https://openalex.org/I87445476","display_name":"Xi'an Jiaotong University","ror":"https://ror.org/017zhmm22","country_code":"CN","type":"education","lineage":["https://openalex.org/I87445476"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chen Yang","raw_affiliation_strings":["School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China"],"raw_orcid":"https://orcid.org/0000-0002-8221-7670","affiliations":[{"raw_affiliation_string":"School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, Shaanxi, China","institution_ids":["https://openalex.org/I87445476"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5101892407"],"corresponding_institution_ids":["https://openalex.org/I87445476"],"apc_list":null,"apc_paid":null,"fwci":0.3535,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.56297692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"33","issue":"2","first_page":"588","last_page":"592"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9117000102996826,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9117000102996826,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6897537708282471},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6881500482559204},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.627408504486084},{"id":"https://openalex.org/keywords/pairwise-comparison","display_name":"Pairwise comparison","score":0.6041368842124939},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5731807947158813},{"id":"https://openalex.org/keywords/group","display_name":"Group (periodic table)","score":0.5340356826782227},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4618116617202759},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29637736082077026},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08905106782913208}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6897537708282471},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6881500482559204},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.627408504486084},{"id":"https://openalex.org/C184898388","wikidata":"https://www.wikidata.org/wiki/Q1435712","display_name":"Pairwise comparison","level":2,"score":0.6041368842124939},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5731807947158813},{"id":"https://openalex.org/C2781311116","wikidata":"https://www.wikidata.org/wiki/Q83306","display_name":"Group (periodic table)","level":2,"score":0.5340356826782227},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4618116617202759},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29637736082077026},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08905106782913208},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2024.3465010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3465010","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G963865091","display_name":null,"funder_award_id":"62176206","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1513904472","https://openalex.org/W2031533839","https://openalex.org/W2067507719","https://openalex.org/W2106970188","https://openalex.org/W2177209050","https://openalex.org/W2768174108","https://openalex.org/W2953289753","https://openalex.org/W3164170653","https://openalex.org/W4226334377","https://openalex.org/W4285264388","https://openalex.org/W4295872570","https://openalex.org/W4312563345","https://openalex.org/W4312578262","https://openalex.org/W4382119118","https://openalex.org/W4384787353","https://openalex.org/W4393144920","https://openalex.org/W6778434676"],"related_works":["https://openalex.org/W2487162673","https://openalex.org/W2793211469","https://openalex.org/W2949152769","https://openalex.org/W4372354731","https://openalex.org/W2942366970","https://openalex.org/W2807634898","https://openalex.org/W1692008701","https://openalex.org/W2597588799","https://openalex.org/W4401278057","https://openalex.org/W2038503502"],"abstract_inverted_index":{"Polynomial":[0],"multiplication":[1],"is":[2,20,45,77,86],"a":[3,59,80],"significant":[4],"bottleneck":[5],"in":[6,52],"mainstream":[7],"postquantum":[8],"cryptography":[9],"(PQC)":[10],"schemes.":[11],"To":[12],"speed":[13],"it":[14,44],"up,":[15],"number":[16],"theoretic":[17],"transform":[18],"(NTT)":[19],"widely":[21],"used,":[22],"which":[23],"decreases":[24],"the":[25,122],"time":[26,152],"complexity":[27],"from":[28],"<inline-formula":[29,36,100,130,142],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[30,37,101,131,143],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[31,38,102,132,144],"<tex-math":[32,39,103,133,145],"notation=\"LaTeX\">${O}(n^{2})$":[33],"</tex-math></inline-formula>":[34,105,136,148],"to":[35,47,88,121,129,141],"notation=\"LaTeX\">$O[n\\log":[40],"_{2}(n)]$":[41],"</tex-math></inline-formula>.":[42],"However,":[43],"challenging":[46],"ensure":[48],"optimal":[49],"hardware":[50],"efficiency":[51],"conjunction":[53],"with":[54],"scalability.":[55],"This":[56],"brief":[57],"proposes":[58],"novel":[60],"pipelined":[61],"NTT/inverse-NTT":[62],"(INTT)":[63],"architecture":[64,115,126],"on":[65,108,150],"field-programmable":[66],"gate":[67],"array":[68],"(FPGA).":[69],"A":[70],"group-based":[71],"pairwise":[72],"memory":[73],"access":[74],"(GPMA)":[75],"scheme":[76],"proposed,":[78],"and":[79,82,97,139],"scratchpad":[81],"reordering":[83],"unit":[84],"(SRU)":[85],"designed":[87],"form":[89],"an":[90],"efficient":[91],"dataflow":[92],"that":[93],"simplifies":[94],"control":[95],"units":[96],"achieves":[98,127],"almost":[99],"notation=\"LaTeX\">$n/2$":[104],"processing":[106],"cycles":[107],"average":[109],"for":[110],"n-point":[111],"NTT.":[112],"Moreover,":[113],"our":[114,125],"can":[116],"support":[117],"varying":[118],"parameters.":[119],"Compared":[120],"state-of-the-art":[123],"works,":[124],"up":[128,140],"notation=\"LaTeX\">$4.8\\times":[134],"$":[135,147],"latency":[137],"improvements":[138,149],"notation=\"LaTeX\">$4.3\\times":[146],"area":[151],"product":[153],"(ATP).":[154]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2025-12-27T23:08:20.325037","created_date":"2025-10-10T00:00:00"}