{"id":"https://openalex.org/W4390827932","doi":"https://doi.org/10.1109/tvlsi.2024.3349564","title":"A Wideband Input Buffer Based on Cascade Complementary Source Follower","display_name":"A Wideband Input Buffer Based on Cascade Complementary Source Follower","publication_year":2024,"publication_date":"2024-01-12","ids":{"openalex":"https://openalex.org/W4390827932","doi":"https://doi.org/10.1109/tvlsi.2024.3349564"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2024.3349564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3349564","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021772164","display_name":"Dengquan Li","orcid":"https://orcid.org/0000-0002-9913-4644"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Dengquan Li","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-9913-4644","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073530854","display_name":"Feng Tian","orcid":"https://orcid.org/0000-0001-7140-4844"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tian Feng","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065553255","display_name":"Jiale Ding","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiale Ding","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029781634","display_name":"Yi Shen","orcid":"https://orcid.org/0000-0002-2586-3772"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yi Shen","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-2586-3772","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100635138","display_name":"Shubin Liu","orcid":"https://orcid.org/0000-0002-9942-0069"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-9942-0069","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039575274","display_name":"Zhangming Zhu","orcid":"https://orcid.org/0000-0002-7764-1928"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhangming Zhu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-7764-1928","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2471,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.87018915,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"32","issue":"5","first_page":"962","last_page":"966"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.7402977347373962},{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.6659360527992249},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5990971922874451},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.5965378284454346},{"id":"https://openalex.org/keywords/cascade","display_name":"Cascade","score":0.5726543664932251},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.520188570022583},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.5071594715118408},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.499786376953125},{"id":"https://openalex.org/keywords/buffer-amplifier","display_name":"Buffer amplifier","score":0.48947060108184814},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.4892999827861786},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.47751584649086},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.47645998001098633},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4544506371021271},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.41609466075897217},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3609634041786194},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3196510672569275},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14851605892181396},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09804481267929077}],"concepts":[{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.7402977347373962},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.6659360527992249},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5990971922874451},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.5965378284454346},{"id":"https://openalex.org/C34146451","wikidata":"https://www.wikidata.org/wiki/Q5048094","display_name":"Cascade","level":2,"score":0.5726543664932251},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.520188570022583},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.5071594715118408},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.499786376953125},{"id":"https://openalex.org/C127749002","wikidata":"https://www.wikidata.org/wiki/Q978470","display_name":"Buffer amplifier","level":4,"score":0.48947060108184814},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.4892999827861786},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.47751584649086},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.47645998001098633},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4544506371021271},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.41609466075897217},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3609634041786194},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3196510672569275},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14851605892181396},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09804481267929077},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2024.3349564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2024.3349564","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7300000190734863}],"awards":[{"id":"https://openalex.org/G1770443930","display_name":null,"funder_award_id":"62274129","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2320218852","display_name":null,"funder_award_id":"62021004","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2351528596","display_name":null,"funder_award_id":"62227816","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4064990617","display_name":null,"funder_award_id":"QTZX23075","funder_id":"https://openalex.org/F4320335787","funder_display_name":"Fundamental Research Funds for the Central Universities"},{"id":"https://openalex.org/G4113703957","display_name":null,"funder_award_id":"62090042","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320335787","display_name":"Fundamental Research Funds for the Central Universities","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W2063492900","https://openalex.org/W2073848487","https://openalex.org/W2133751064","https://openalex.org/W2138536318","https://openalex.org/W2291503911","https://openalex.org/W2791187414","https://openalex.org/W2800737594","https://openalex.org/W2906404755","https://openalex.org/W2998298423","https://openalex.org/W3028717114","https://openalex.org/W3042423334","https://openalex.org/W3044284751","https://openalex.org/W3116209544","https://openalex.org/W3127921087","https://openalex.org/W3180157116","https://openalex.org/W3198462881","https://openalex.org/W4200569567","https://openalex.org/W4206180590","https://openalex.org/W4239486830","https://openalex.org/W4285133984","https://openalex.org/W4310720392","https://openalex.org/W4320015657","https://openalex.org/W4385624911"],"related_works":["https://openalex.org/W3123985664","https://openalex.org/W1965786156","https://openalex.org/W2098366763","https://openalex.org/W4206743490","https://openalex.org/W3127766301","https://openalex.org/W2101187277","https://openalex.org/W2073258809","https://openalex.org/W4247677020","https://openalex.org/W2131925274","https://openalex.org/W2430807860"],"abstract_inverted_index":{"A":[0],"highly":[1],"linear":[2],"input":[3,31,41,57,103,125],"buffer":[4,32,42,58,104],"is":[5,53,59],"crucial":[6],"for":[7],"high-speed":[8],"and":[9,20,38,67,84,93,111,114,120,138],"high-resolution":[10],"analog-to-digital":[11],"converters":[12],"(ADCs)":[13],"since":[14],"it":[15],"isolates":[16],"the":[17,27,30,91,101,106],"kickback":[18],"noise":[19],"package":[21],"inductance.":[22],"Several":[23],"important":[24],"factors":[25],"affecting":[26],"linearity":[28,45],"of":[29,61,118],"are":[33,87],"analyzed":[34],"in":[35,97],"this":[36],"brief,":[37],"a":[39,62,98,112],"wideband":[40],"with":[43,123],"high":[44],"based":[46],"on":[47],"cascade":[48],"complementary":[49],"source":[50,64,70],"follower":[51,65,71],"(CCSF)":[52],"proposed.":[54],"This":[55],"cascaded":[56],"composed":[60],"pMOS":[63],"(PSF)":[66],"an":[68],"nMOS":[69],"(NSF).":[72],"Compensation":[73],"capacitor,":[74],"assisted":[75],"operational":[76],"amplifier":[77],"(opamp),":[78],"bootstrapped-capacitor":[79],"level-shifting":[80],"circuit,":[81],"current":[82],"amplifier,":[83],"optimization":[85],"strategies":[86],"utilized":[88],"to":[89],"extend":[90],"bandwidth":[92],"reduce":[94],"distortion.":[95],"Designed":[96],"65-nm":[99],"CMOS,":[100],"CCSF":[102],"achieves":[105],"spurious-free":[107],"dynamic":[108],"range":[109],"(SFDR)":[110],"signal-to-noise":[113],"distortion":[115],"ratio":[116],"(SNDR)":[117],"76.6":[119],"58.1":[121],"dB":[122],"1.9-GHz":[124],"frequency,":[126],"respectively.":[127],"It":[128],"occupies":[129],"0.0155":[130],"mm":[131],"<inline-formula":[132],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[133],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[134],"<tex-math":[135],"notation=\"LaTeX\">$^2$</tex-math>":[136],"</inline-formula>":[137],"consumes":[139],"27":[140],"mW":[141],"at":[142],"2.5":[143],"V.":[144]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":4}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}