{"id":"https://openalex.org/W4389403448","doi":"https://doi.org/10.1109/tvlsi.2023.3336804","title":"Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System","display_name":"Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System","publication_year":2023,"publication_date":"2023-12-06","ids":{"openalex":"https://openalex.org/W4389403448","doi":"https://doi.org/10.1109/tvlsi.2023.3336804"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2023.3336804","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2023.3336804","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048092191","display_name":"Sureum Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sureum Choi","raw_affiliation_strings":["College of Engineering, Inha University, Incheon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Engineering, Inha University, Incheon, South Korea","institution_ids":["https://openalex.org/I191879574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113064654","display_name":"Daejin Han","orcid":null},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Daejin Han","raw_affiliation_strings":["College of Engineering, Inha University, Incheon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Engineering, Inha University, Incheon, South Korea","institution_ids":["https://openalex.org/I191879574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030190154","display_name":"Chanyeong Choi","orcid":null},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chanyeong Choi","raw_affiliation_strings":["College of Engineering, Inha University, Incheon, South Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Engineering, Inha University, Incheon, South Korea","institution_ids":["https://openalex.org/I191879574"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051268559","display_name":"Yeongkyo Seo","orcid":"https://orcid.org/0000-0001-7931-6275"},"institutions":[{"id":"https://openalex.org/I191879574","display_name":"Inha University","ror":"https://ror.org/01easw929","country_code":"KR","type":"education","lineage":["https://openalex.org/I191879574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yeongkyo Seo","raw_affiliation_strings":["College of Engineering, Inha University, Incheon, South Korea"],"raw_orcid":"https://orcid.org/0000-0001-7931-6275","affiliations":[{"raw_affiliation_string":"College of Engineering, Inha University, Incheon, South Korea","institution_ids":["https://openalex.org/I191879574"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I191879574"],"apc_list":null,"apc_paid":null,"fwci":0.5807,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.67020567,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"32","issue":"2","first_page":"245","last_page":"255"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10049","display_name":"Magnetic properties of thin films","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.665172278881073},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.6248521208763123},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6059131026268005},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.47298988699913025},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4347917437553406},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4280407726764679},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37228256464004517},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33093351125717163},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2795163094997406},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2365422546863556},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2217211127281189},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.13430508971214294},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09068045020103455}],"concepts":[{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.665172278881073},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.6248521208763123},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6059131026268005},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.47298988699913025},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4347917437553406},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4280407726764679},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37228256464004517},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33093351125717163},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2795163094997406},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2365422546863556},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2217211127281189},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.13430508971214294},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09068045020103455},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2023.3336804","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2023.3336804","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G166410411","display_name":null,"funder_award_id":"NRF-2020M3H2A1076786","funder_id":"https://openalex.org/F4320322030","funder_display_name":"Ministry of Science, ICT and Future Planning"},{"id":"https://openalex.org/G2545269038","display_name":null,"funder_award_id":"NRF-2021M3F3A2A01037531","funder_id":"https://openalex.org/F4320322030","funder_display_name":"Ministry of Science, ICT and Future Planning"},{"id":"https://openalex.org/G398471086","display_name":null,"funder_award_id":"NRF-2022M3I7A2079155","funder_id":"https://openalex.org/F4320322030","funder_display_name":"Ministry of Science, ICT and Future Planning"},{"id":"https://openalex.org/G6143419704","display_name":null,"funder_award_id":"20009972","funder_id":"https://openalex.org/F4320321681","funder_display_name":"Ministry of Trade, Industry and Energy"}],"funders":[{"id":"https://openalex.org/F4320321681","display_name":"Ministry of Trade, Industry and Energy","ror":"https://ror.org/008nkqk13"},{"id":"https://openalex.org/F4320322030","display_name":"Ministry of Science, ICT and Future Planning","ror":"https://ror.org/032e49973"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":53,"referenced_works":["https://openalex.org/W1504464452","https://openalex.org/W1553965204","https://openalex.org/W1604973310","https://openalex.org/W1686183427","https://openalex.org/W1980507265","https://openalex.org/W1985887979","https://openalex.org/W2003346399","https://openalex.org/W2019945763","https://openalex.org/W2035925590","https://openalex.org/W2057386187","https://openalex.org/W2076063813","https://openalex.org/W2087461437","https://openalex.org/W2096199318","https://openalex.org/W2096470311","https://openalex.org/W2109596721","https://openalex.org/W2128432504","https://openalex.org/W2131763976","https://openalex.org/W2134331449","https://openalex.org/W2142436896","https://openalex.org/W2157017433","https://openalex.org/W2176123422","https://openalex.org/W2188761345","https://openalex.org/W2323009761","https://openalex.org/W2336168666","https://openalex.org/W2528596247","https://openalex.org/W2552243702","https://openalex.org/W2742694477","https://openalex.org/W2783525259","https://openalex.org/W2803914619","https://openalex.org/W2897961390","https://openalex.org/W2899637031","https://openalex.org/W2933452742","https://openalex.org/W2966424439","https://openalex.org/W2971958737","https://openalex.org/W2976137532","https://openalex.org/W3000651435","https://openalex.org/W3016245653","https://openalex.org/W3049223108","https://openalex.org/W3089664868","https://openalex.org/W3093817935","https://openalex.org/W3124716720","https://openalex.org/W3144904247","https://openalex.org/W3149633442","https://openalex.org/W3172819050","https://openalex.org/W3206226376","https://openalex.org/W4205230840","https://openalex.org/W4285292207","https://openalex.org/W4290716141","https://openalex.org/W4294691012","https://openalex.org/W4308575307","https://openalex.org/W4320005519","https://openalex.org/W4360607286","https://openalex.org/W6687026183"],"related_works":["https://openalex.org/W2108167458","https://openalex.org/W583900352","https://openalex.org/W2357425846","https://openalex.org/W2091329789","https://openalex.org/W1873584906","https://openalex.org/W2376726667","https://openalex.org/W2347826081","https://openalex.org/W4387088711","https://openalex.org/W2558703803","https://openalex.org/W2993278091"],"abstract_inverted_index":{"This":[0,191],"article":[1],"presents":[2],"a":[3,28,91,97,101],"layout-aware":[4],"area":[5,66,131,160,182],"optimization":[6,38],"methodology":[7],"for":[8,27,85,100,204],"transposable":[9,18,86],"spin-transfer":[10],"torque":[11],"magnetic":[12,102],"random":[13],"access":[14,79],"memory":[15],"(STT-MRAM).":[16],"Although":[17],"STT-MRAM":[19,87],"achieves":[20,123,178],"high":[21],"performance":[22],"in":[23,34,90,108,133,162,207],"processing-in-memory":[24],"(PIM)":[25],"systems":[26],"spiking":[29],"neural":[30],"network":[31],"(SNN),":[32],"challenges":[33],"layout":[35,54,71,83,121,138,176,189,197],"design":[36,55,72,122,145,177,198,211],"and":[37,152,199,216],"remain":[39],"owing":[40],"to":[41,57,74],"the":[42,64,75,109,157,163,186,209],"vertical":[43],"arrangement":[44],"of":[45,68,77,147],"its":[46],"two":[47,78],"wordlines":[48],"(WLs).":[49],"We":[50,61],"propose":[51],"three":[52],"different":[53],"techniques":[56],"address":[58],"these":[59],"challenges.":[60],"also":[62],"analyze":[63],"cell":[65,125,154,159],"changes":[67],"our":[69,114,170,195],"proposed":[70,82,115,137,171,188,196],"according":[73],"width":[76],"transistors.":[80],"The":[81],"designs":[84],"are":[88],"implemented":[89],"28-nm":[92],"CMOS":[93],"technology":[94],"coupled":[95],"with":[96,118,127,135,174,185],"SPICE-compatible":[98],"model":[99],"tunnel":[103,155],"junction.":[104],"Results":[105],"show":[106],"that":[107,194,212],"metal":[110,119],"pitch":[111],"limited":[112],"region,":[113],"perpendicular":[116],"poly":[117,173],"column-WL-based":[120],"minimum":[124],"area,":[126],"at":[128,179],"least":[129,180],"5.3%":[130],"savings":[132,183],"comparison":[134],"other":[136,187],"designs.":[139,190],"Furthermore,":[140],"by":[141],"targeting":[142],"an":[143],"identical":[144],"specification":[146],"35%":[148],"write":[149],"margin":[150],"(WM)":[151],"160%":[153],"magnetoresistance,":[156],"resulting":[158],"falls":[161],"transistor":[164],"width-limited":[165],"region.":[166],"In":[167],"this":[168],"case,":[169],"parallel":[172],"metal-WL-based":[175],"21%":[181],"compared":[184],"result":[192],"demonstrates":[193],"analysis":[200],"offer":[201],"valuable":[202],"insights":[203],"circuit":[205],"designers":[206],"selecting":[208],"optimal":[210],"meets":[213],"target":[214],"specifications":[215],"requirements.":[217]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
