{"id":"https://openalex.org/W4388520120","doi":"https://doi.org/10.1109/tvlsi.2023.3328978","title":"Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS","display_name":"Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS","publication_year":2023,"publication_date":"2023-11-09","ids":{"openalex":"https://openalex.org/W4388520120","doi":"https://doi.org/10.1109/tvlsi.2023.3328978"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2023.3328978","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/tvlsi.2023.3328978","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101771348","display_name":"Shourya Gupta","orcid":"https://orcid.org/0000-0002-1804-5202"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shourya Gupta","raw_affiliation_strings":["Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-1804-5202","affiliations":[{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100386624","display_name":"Shuo Li","orcid":"https://orcid.org/0000-0002-2024-2002"},"institutions":[{"id":"https://openalex.org/I32971472","display_name":"Yale University","ror":"https://ror.org/03v76x132","country_code":"US","type":"education","lineage":["https://openalex.org/I32971472"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shuo Li","raw_affiliation_strings":["Department of Electrical Engineering, Yale University, New Haven, CT, USA"],"raw_orcid":"https://orcid.org/0000-0002-2024-2002","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Yale University, New Haven, CT, USA","institution_ids":["https://openalex.org/I32971472"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benton H. Calhoun","raw_affiliation_strings":["Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA"],"raw_orcid":"https://orcid.org/0000-0002-3770-5050","affiliations":[{"raw_affiliation_string":"Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USA","institution_ids":["https://openalex.org/I51556381"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1161,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.43569999,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":97},"biblio":{"volume":"32","issue":"1","first_page":"190","last_page":"194"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7579847574234009},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.6718550324440002},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6699475049972534},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6563107371330261},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6077398061752319},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5874146223068237},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5748730897903442},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5527867674827576},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.496570885181427},{"id":"https://openalex.org/keywords/figure-of-merit","display_name":"Figure of merit","score":0.447751522064209},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.43776363134384155},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4375031292438507},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4248808026313782},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.42236945033073425},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3803821802139282},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29854050278663635},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23032057285308838}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7579847574234009},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.6718550324440002},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6699475049972534},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6563107371330261},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6077398061752319},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5874146223068237},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5748730897903442},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5527867674827576},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.496570885181427},{"id":"https://openalex.org/C130277099","wikidata":"https://www.wikidata.org/wiki/Q3676605","display_name":"Figure of merit","level":2,"score":0.447751522064209},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.43776363134384155},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4375031292438507},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4248808026313782},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.42236945033073425},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3803821802139282},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29854050278663635},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23032057285308838},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2023.3328978","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/tvlsi.2023.3328978","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3686978712","display_name":null,"funder_award_id":"FA8650-18-2-7844","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2141495440","https://openalex.org/W2551453206","https://openalex.org/W2768557657","https://openalex.org/W2790621319","https://openalex.org/W2945221971","https://openalex.org/W2999213071","https://openalex.org/W3015876354","https://openalex.org/W3016214307","https://openalex.org/W3129396745","https://openalex.org/W3163113027","https://openalex.org/W3186013690","https://openalex.org/W3186111946","https://openalex.org/W4232735308","https://openalex.org/W4286367833","https://openalex.org/W4312450968"],"related_works":["https://openalex.org/W4242619554","https://openalex.org/W4321510758","https://openalex.org/W2170430628","https://openalex.org/W2023977730","https://openalex.org/W2110634429","https://openalex.org/W2246013696","https://openalex.org/W1515835798","https://openalex.org/W2170433636","https://openalex.org/W4289655491","https://openalex.org/W1975370182"],"abstract_inverted_index":{"The":[0],"design":[1,30,73,81],"and":[2,11,23,29,32,82,93,126],"verification":[3],"process":[4,84],"for":[5,97],"analog":[6,55,91],"circuits":[7,22,75],"can":[8],"be":[9],"long":[10],"tedious,":[12],"wherein":[13],"designers":[14],"rely":[15],"heavily":[16],"on":[17],"manual":[18],"effort":[19],"to":[20,40,72,115,128,137],"create":[21],"draw":[24],"layouts,":[25],"thereby":[26,60],"limiting":[27],"turn-around-time":[28],"scale":[31],"increasing":[33],"costs.":[34],"Various":[35],"previous":[36],"works":[37],"have":[38],"tried":[39],"solve":[41],"this":[42,64],"issue":[43],"by":[44],"leveraging":[45],"digital":[46,58,69],"automated":[47],"place-and-route":[48],"(APR)":[49],"tools,":[50],"but":[51],"they":[52],"involve":[53],"replacing":[54],"elements":[56],"with":[57,135],"counterparts,":[59],"dampening":[61],"performance.":[62],"In":[63],"work,":[65],"we":[66],"propose":[67],"a":[68,120],"flow-based":[70],"approach":[71],"all-analog":[74],"that":[76,109],"dramatically":[77],"speeds":[78],"up":[79,114,127],"the":[80,87,95,110],"layout":[83],"while":[85],"retaining":[86],"benefits":[88],"of":[89,123],"true":[90],"topologies":[92],"demonstrate":[94],"performance":[96],"three":[98],"low-dropout":[99],"regulators":[100],"(LDOs).":[101],"Fabricated":[102],"in":[103,131],"65-nm":[104],"CMOS,":[105],"measurement":[106],"results":[107],"show":[108],"generated":[111],"LDOs":[112],"achieve":[113],"99.95%":[116],"peak":[117],"current":[118],"efficiency,":[119],"figure-of-merit":[121],"(FOM)":[122],"4.6":[124],"ps,":[125],"63.93%":[129],"reduction":[130],"input":[132],"offset":[133],"variability":[134],"respect":[136],"their":[138],"manually":[139],"designed":[140],"counterparts.":[141]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}
