{"id":"https://openalex.org/W4386736627","doi":"https://doi.org/10.1109/tvlsi.2023.3311178","title":"PALS: Distributed Gradient Clocking on Chip","display_name":"PALS: Distributed Gradient Clocking on Chip","publication_year":2023,"publication_date":"2023-09-14","ids":{"openalex":"https://openalex.org/W4386736627","doi":"https://doi.org/10.1109/tvlsi.2023.3311178"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2023.3311178","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2023.3311178","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://hal.science/hal-04266029/document","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006330730","display_name":"Johannes Bund","orcid":null},"institutions":[{"id":"https://openalex.org/I4210128801","display_name":"Helmholtz Center for Information Security","ror":"https://ror.org/02njgxr09","country_code":"DE","type":"facility","lineage":["https://openalex.org/I1305996414","https://openalex.org/I4210128801"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Johannes Bund","raw_affiliation_strings":["CISPA Helmholtz Center for Information Security, Saarbrücken, Germany"],"raw_orcid":"https://orcid.org/0000-0002-1108-1091","affiliations":[{"raw_affiliation_string":"CISPA Helmholtz Center for Information Security, Saarbrücken, Germany","institution_ids":["https://openalex.org/I4210128801"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049530550","display_name":"Matthias F\u00fcgger","orcid":"https://orcid.org/0000-0001-5765-0301"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I29607241","display_name":"\u00c9cole Normale Sup\u00e9rieure - PSL","ror":"https://ror.org/05a0dhs15","country_code":"FR","type":"other","lineage":["https://openalex.org/I2746051580","https://openalex.org/I29607241"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Matthias F\u00fcgger","raw_affiliation_strings":["French National Centre for Scientific Research (CNRS), Formal Methods Laboratory (LMF), École Normale Supérieure (ENS) Paris-Saclay, Université Paris-Saclay, Gif-sur-Yvette, France"],"raw_orcid":"https://orcid.org/0000-0001-5765-0301","affiliations":[{"raw_affiliation_string":"French National Centre for Scientific Research (CNRS), Formal Methods Laboratory (LMF), École Normale Supérieure (ENS) Paris-Saclay, Université Paris-Saclay, Gif-sur-Yvette, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I29607241"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007248799","display_name":"Moti Medina","orcid":"https://orcid.org/0000-0002-5572-3754"},"institutions":[{"id":"https://openalex.org/I13955877","display_name":"Bar-Ilan University","ror":"https://ror.org/03kgsv495","country_code":"IL","type":"education","lineage":["https://openalex.org/I13955877"]}],"countries":["IL"],"is_corresponding":false,"raw_author_name":"Moti Medina","raw_affiliation_strings":["Engineering Faculty, Bar-Ilan University, Ramat Gan, Israel"],"raw_orcid":"https://orcid.org/0000-0002-5572-3754","affiliations":[{"raw_affiliation_string":"Engineering Faculty, Bar-Ilan University, Ramat Gan, Israel","institution_ids":["https://openalex.org/I13955877"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3981,"has_fulltext":true,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61357191,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"31","issue":"11","first_page":"1740","last_page":"1753"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7267433404922485},{"id":"https://openalex.org/keywords/handshaking","display_name":"Handshaking","score":0.6633676290512085},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6355688571929932},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.605273962020874},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5432655811309814},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5344563722610474},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5139471888542175},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5019114017486572},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.47853025794029236},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.43581101298332214},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3910963535308838},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3821977376937866},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3525874614715576},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2698715329170227},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.21194297075271606},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12009426951408386}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7267433404922485},{"id":"https://openalex.org/C58861099","wikidata":"https://www.wikidata.org/wiki/Q548838","display_name":"Handshaking","level":2,"score":0.6633676290512085},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6355688571929932},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.605273962020874},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5432655811309814},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5344563722610474},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5139471888542175},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5019114017486572},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.47853025794029236},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.43581101298332214},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3910963535308838},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3821977376937866},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3525874614715576},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2698715329170227},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.21194297075271606},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12009426951408386},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tvlsi.2023.3311178","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2023.3311178","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-04266029v1","is_oa":true,"landing_page_url":"https://hal.science/hal-04266029","pdf_url":"https://hal.science/hal-04266029/document","source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31 (11), pp.1740-1753. ⟨10.1109/TVLSI.2023.3311178⟩","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-04266029v1","is_oa":true,"landing_page_url":"https://hal.science/hal-04266029","pdf_url":"https://hal.science/hal-04266029/document","source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023, 31 (11), pp.1740-1753. ⟨10.1109/TVLSI.2023.3311178⟩","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1426680658","display_name":"A Theory of Reliable Hardware","funder_award_id":"716562","funder_id":"https://openalex.org/F4320338335","funder_display_name":"H2020 European Research Council"},{"id":"https://openalex.org/G1513065152","display_name":null,"funder_award_id":"867/19","funder_id":"https://openalex.org/F4320322252","funder_display_name":"Israel Science Foundation"},{"id":"https://openalex.org/G2155879968","display_name":"Distributed Algorithms for Microbiological Systems","funder_award_id":"ANR-21-CE48-0003","funder_id":"https://openalex.org/F4320320883","funder_display_name":"Agence Nationale de la Recherche"},{"id":"https://openalex.org/G7842005466","display_name":null,"funder_award_id":"Horizon 2020","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320320883","display_name":"Agence Nationale de la Recherche","ror":"https://ror.org/00rbzpz17"},{"id":"https://openalex.org/F4320322252","display_name":"Israel Science Foundation","ror":"https://ror.org/04sazxf24"},{"id":"https://openalex.org/F4320338335","display_name":"H2020 European Research Council","ror":"https://ror.org/0472cxd90"}],"has_content":{"pdf":true,"grobid_xml":false},"content_urls":{"pdf":"https://content.openalex.org/works/W4386736627.pdf"},"referenced_works_count":30,"referenced_works":["https://openalex.org/W1414112296","https://openalex.org/W1609287256","https://openalex.org/W1943426535","https://openalex.org/W1975638748","https://openalex.org/W2012262513","https://openalex.org/W2029005287","https://openalex.org/W2033142981","https://openalex.org/W2037181413","https://openalex.org/W2038591001","https://openalex.org/W2054095206","https://openalex.org/W2101113282","https://openalex.org/W2110142332","https://openalex.org/W2111207983","https://openalex.org/W2134829921","https://openalex.org/W2143420037","https://openalex.org/W2150415477","https://openalex.org/W2162372871","https://openalex.org/W2167308418","https://openalex.org/W2167873583","https://openalex.org/W2646303175","https://openalex.org/W2767956243","https://openalex.org/W2963331517","https://openalex.org/W2977344565","https://openalex.org/W2981928219","https://openalex.org/W3021040759","https://openalex.org/W3081868892","https://openalex.org/W3172924753","https://openalex.org/W4360606536","https://openalex.org/W6628375995","https://openalex.org/W6663687029"],"related_works":["https://openalex.org/W1507726314","https://openalex.org/W847004690","https://openalex.org/W2147289961","https://openalex.org/W2031867410","https://openalex.org/W4241143485","https://openalex.org/W2565835957","https://openalex.org/W2767138966","https://openalex.org/W2065796241","https://openalex.org/W2385857077","https://openalex.org/W1526416583"],"abstract_inverted_index":{"Consider":[0],"an":[1],"arbitrary":[2],"network":[3],"of":[4,59,65,111,119,158],"communicating":[5],"modules":[6,104,124],"on":[7,90,161],"a":[8,12,20,31,40,66,79,91,100,129,142],"chip,":[9],"each":[10,58],"requiring":[11],"local":[13,32,106],"signal":[14],"telling":[15],"it":[16,38],"when":[17],"to":[18,28,127],"execute":[19],"computational":[21],"step.":[22],"There":[23],"are":[24,72,113,125],"three":[25],"common":[26],"solutions":[27,61],"generating":[29],"such":[30],"clock":[33,43,94,136],"signal:":[34],"1)":[35],"by":[36,46,52],"deriving":[37],"from":[39,141],"single,":[41],"central":[42],"source;":[44],"2)":[45],"local,":[47],"free-running":[48,120],"oscillators;":[49],"or":[50,75],"3)":[51],"handshaking":[53],"between":[54,86],"neighboring":[55,123],"modules.":[56],"Conceptually,":[57],"these":[60,87],"is":[62],"the":[63,108,162],"result":[64],"perceived":[67],"dichotomy":[68],"in":[69],"which":[70,112],"(sub)systems":[71],"either":[73],"clocked":[74],"asynchronous.":[76],"We":[77],"present":[78],"solution":[80],"and":[81],"its":[82],"implementation":[83],"that":[84],"lies":[85],"extremes.":[88],"Based":[89],"distributed":[92],"gradient":[93],"synchronization":[95],"(GCS)":[96],"algorithm,":[97],"we":[98],"show":[99],"novel":[101],"design":[102],"providing":[103],"with":[105],"clocks,":[107],"frequency":[109],"bounds":[110,157],"almost":[114],"as":[115,117],"good":[116],"those":[118],"oscillators,":[121],"yet":[122],"guaranteed":[126],"have":[128],"phase":[130,163],"offset":[131,164],"substantially":[132],"smaller":[133],"than":[134],"one":[135],"cycle.":[137],"Concretely,":[138],"parameters":[139],"obtained":[140],"15-nm":[143],"application":[144],"specific":[145],"integrated":[146],"circuit":[147],"(ASIC)":[148],"simulation":[149],"running":[150],"at":[151],"2":[152],"GHz":[153],"yield":[154],"mathematical":[155],"worst-case":[156],"20":[159],"ps":[160],"for":[165],"a$32\\,\\,":[166],"\\times":[167],"32$node":[168],"grid":[169],"network.":[170]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}