{"id":"https://openalex.org/W4386262125","doi":"https://doi.org/10.1109/tvlsi.2023.3305915","title":"Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic","display_name":"Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic","publication_year":2023,"publication_date":"2023-08-29","ids":{"openalex":"https://openalex.org/W4386262125","doi":"https://doi.org/10.1109/tvlsi.2023.3305915"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2023.3305915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2023.3305915","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5092713381","display_name":"R. Malmir","orcid":null},"institutions":[{"id":"https://openalex.org/I119025939","display_name":"Shahed University","ror":"https://ror.org/01e8ff003","country_code":"IR","type":"education","lineage":["https://openalex.org/I119025939"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"R. Malmir","raw_affiliation_strings":["Department of Electrical Engineering, Shahed University, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shahed University, Tehran, Iran","institution_ids":["https://openalex.org/I119025939"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036799779","display_name":"M. B. Ghaznavi\u2010Ghoushchi","orcid":"https://orcid.org/0000-0001-7026-9476"},"institutions":[{"id":"https://openalex.org/I119025939","display_name":"Shahed University","ror":"https://ror.org/01e8ff003","country_code":"IR","type":"education","lineage":["https://openalex.org/I119025939"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"M. B. Ghaznavi-Ghoushchi","raw_affiliation_strings":["Department of Electrical Engineering, Shahed University, Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shahed University, Tehran, Iran","institution_ids":["https://openalex.org/I119025939"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5092713381"],"corresponding_institution_ids":["https://openalex.org/I119025939"],"apc_list":null,"apc_paid":null,"fwci":0.6694,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68773074,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"31","issue":"11","first_page":"1675","last_page":"1685"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8547533750534058},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.6858350038528442},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6423505544662476},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5999745726585388},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.5724912285804749},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.5513944625854492},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5350314974784851},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.524311900138855},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5095746517181396},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.44441524147987366},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4323882460594177},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4296777844429016},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.42681077122688293},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4228476583957672},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.42185717821121216},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3963300883769989},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.276288777589798},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.26614898443222046},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2563479244709015},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2535340189933777},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2440166175365448},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.21402955055236816}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8547533750534058},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.6858350038528442},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6423505544662476},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5999745726585388},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.5724912285804749},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5513944625854492},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5350314974784851},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.524311900138855},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5095746517181396},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.44441524147987366},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4323882460594177},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4296777844429016},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.42681077122688293},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4228476583957672},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.42185717821121216},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3963300883769989},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.276288777589798},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.26614898443222046},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2563479244709015},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2535340189933777},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2440166175365448},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.21402955055236816},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2023.3305915","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2023.3305915","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.75,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1535389693","https://openalex.org/W1565379800","https://openalex.org/W1997433601","https://openalex.org/W2000260960","https://openalex.org/W2014694497","https://openalex.org/W2020854458","https://openalex.org/W2032786864","https://openalex.org/W2069169282","https://openalex.org/W2099144852","https://openalex.org/W2119935308","https://openalex.org/W2131698501","https://openalex.org/W2134830891","https://openalex.org/W2135311156","https://openalex.org/W2146638301","https://openalex.org/W2147649838","https://openalex.org/W2612120119","https://openalex.org/W2741337042","https://openalex.org/W2922160289","https://openalex.org/W2991599027","https://openalex.org/W3016883187","https://openalex.org/W3042711247","https://openalex.org/W3134041270","https://openalex.org/W3170871876","https://openalex.org/W4230728857","https://openalex.org/W4252370165","https://openalex.org/W6632154167","https://openalex.org/W6737362722"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2102653533","https://openalex.org/W2058869645","https://openalex.org/W2586049422","https://openalex.org/W2178512053","https://openalex.org/W2020551446","https://openalex.org/W2061966795","https://openalex.org/W1558283416","https://openalex.org/W2112242076","https://openalex.org/W4242766712"],"abstract_inverted_index":{"In":[0,35,129],"this":[1],"article,":[2],"we":[3],"proposed":[4,88,152,207,227,250],"a":[5,21,39,49,91,246],"new":[6],"design":[7,104],"called":[8],"complementary":[9],"fold-interleaved":[10],"multiple-tail":[11],"current":[12,41,81,142],"mode":[13,143],"logic":[14,85,144,153,251],"(CFIMTCML)":[15],"to":[16,55,96,219,234],"implement":[17],"logical":[18],"functions":[19],"with":[20,48,113,135],"fan-in":[22],"higher":[23],"than":[24,164,211],"2.":[25],"This":[26,242],"idea":[27],"is":[28,42,60,70,133,209,245],"implemented":[29,71,134],"by":[30,72],"alternately":[31],"executing":[32],"two":[33],"steps.":[34],"the":[36,53,56,97,131,136,151,172,183,206,212,226,249],"first":[37],"step,":[38],"tail":[40],"divided":[43],"into":[44],"multiple":[45],"currents,":[46],"but":[47],"shallower":[50],"depth":[51],"from":[52],"ground":[54],"common-mode":[57],"point.":[58],"It":[59],"applied":[61],"on":[62],"all":[63],"fully":[64],"stacked":[65],"stages.":[66],"The":[67,87,108,198],"second":[68],"step":[69],"alternating":[73],"nMOS":[74],"and":[75,79,103,121,146,157,168,176,186,228],"pMOS":[76],"differential":[77],"pairs":[78],"utilizing":[80],"mirrors":[82],"in":[83],"adjacent":[84],"levels.":[86],"approach":[89],"allows":[90],"minimum":[92],"power":[93,159],"supply":[94,122],"equal":[95],"conventional":[98,137,165],"MCML":[99],"inverter.":[100],"Analytical":[101],"details":[102],"procedures":[105],"are":[106],"presented.":[107],"method":[109],"has":[110],"been":[111],"validated":[112],"post-layout":[114],"simulations":[115],"considering":[116],"180":[117],"nm":[118],"CMOS":[119],"technology":[120],"voltage":[123],"as":[124,126,182],"low":[125],"0.6":[127,223,238],"V.":[128],"particular,":[130],"SOP_X4":[132],"SCL,":[138,166],"MTCML,":[139,167],"multifolded":[140],"MOS":[141],"(MFMCML),":[145],"CFIMTCML.":[147],"Results":[148],"show":[149],"that":[150],"demonstrates":[154],"90%,":[155],"20%,":[156],"50%":[158],"delay":[160,199],"product":[161],"(PDP)":[162],"reduction":[163,195],"MFMCML,":[169],"respectively.":[170],"Also,":[171],"results":[173],"of":[174,178,196,248],"implementation":[175],"comparison":[177],"other":[179],"gates,":[180],"such":[181],"carry":[184,188],"generator":[185,189],"8-bit":[187],"demonstrate,":[190],"at":[191,202,216,222,231,237],"least":[192],"about":[193],"20%":[194],"PDP.":[197],"increase":[200],"rate":[201],"lower":[203],"voltages":[204],"for":[205,225,240,252],"gates":[208],"slower":[210],"counterparts":[213],"(15":[214],"ps":[215,221,230,236],"1.8":[217,232],"V":[218,224,233,239],"124":[220],"27":[229],"253":[235],"MFMCML).":[241],"mitigated":[243],"degradation":[244],"benefit":[247],"low-noise/low-power":[253],"applications":[254],"demanding":[255],"ultralow":[256],"voltages.":[257]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
