{"id":"https://openalex.org/W4313477054","doi":"https://doi.org/10.1109/tvlsi.2022.3232516","title":"A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration","display_name":"A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration","publication_year":2023,"publication_date":"2023-01-02","ids":{"openalex":"https://openalex.org/W4313477054","doi":"https://doi.org/10.1109/tvlsi.2022.3232516"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2022.3232516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2022.3232516","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051107740","display_name":"Yushen Fu","orcid":"https://orcid.org/0000-0001-6916-0115"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yushen Fu","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019261957","display_name":"Chenyu Huang","orcid":"https://orcid.org/0000-0001-9521-5650"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chengyu Huang","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031300749","display_name":"Limeng Sun","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Limeng Sun","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102082224","display_name":"Weiguang Meng","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weiguang Meng","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100764674","display_name":"Xueqing Li","orcid":"https://orcid.org/0000-0002-8051-3345"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xueqing Li","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023755254","display_name":"Huazhong Yang","orcid":"https://orcid.org/0000-0003-2421-353X"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huazhong Yang","raw_affiliation_strings":["Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, Tsinghua University, Beijing, BNRist, China","institution_ids":["https://openalex.org/I99065089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5051107740"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.8776,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.68766303,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"31","issue":"2","first_page":"199","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.9237737655639648},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6682173013687134},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5329723358154297},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.4918205738067627},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49091464281082153},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.48355361819267273},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.4574339985847473},{"id":"https://openalex.org/keywords/differential-nonlinearity","display_name":"Differential nonlinearity","score":0.44940584897994995},{"id":"https://openalex.org/keywords/digital-to-analog-converter","display_name":"Digital-to-analog converter","score":0.4356761872768402},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.4141744077205658},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4124293923377991},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.32292038202285767},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.3009393811225891},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2646591067314148},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2336324155330658},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15881872177124023}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.9237737655639648},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6682173013687134},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5329723358154297},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.4918205738067627},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49091464281082153},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.48355361819267273},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.4574339985847473},{"id":"https://openalex.org/C71217194","wikidata":"https://www.wikidata.org/wiki/Q575958","display_name":"Differential nonlinearity","level":3,"score":0.44940584897994995},{"id":"https://openalex.org/C2779879419","wikidata":"https://www.wikidata.org/wiki/Q210863","display_name":"Digital-to-analog converter","level":3,"score":0.4356761872768402},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.4141744077205658},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4124293923377991},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.32292038202285767},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.3009393811225891},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2646591067314148},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2336324155330658},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15881872177124023}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2022.3232516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2022.3232516","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.800000011920929,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G5114541946","display_name":null,"funder_award_id":"61934009","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1549004858","https://openalex.org/W1733764130","https://openalex.org/W1993828767","https://openalex.org/W2020846474","https://openalex.org/W2034423388","https://openalex.org/W2036604277","https://openalex.org/W2052612469","https://openalex.org/W2088083354","https://openalex.org/W2089253234","https://openalex.org/W2093095114","https://openalex.org/W2105309396","https://openalex.org/W2117843175","https://openalex.org/W2131805104","https://openalex.org/W2142184691","https://openalex.org/W2147781728","https://openalex.org/W2149655780","https://openalex.org/W2346519112","https://openalex.org/W2400300013","https://openalex.org/W2475869506","https://openalex.org/W2527490636","https://openalex.org/W2592149517","https://openalex.org/W2742693263","https://openalex.org/W2751437525","https://openalex.org/W2789575721","https://openalex.org/W2789669262","https://openalex.org/W2793780905","https://openalex.org/W2892043033","https://openalex.org/W2897737610","https://openalex.org/W2898696738","https://openalex.org/W2929212347","https://openalex.org/W3027920749","https://openalex.org/W3034920226","https://openalex.org/W3107847738","https://openalex.org/W3118066071","https://openalex.org/W3130145184","https://openalex.org/W3137875326","https://openalex.org/W3165872030","https://openalex.org/W3200274002","https://openalex.org/W3209204679","https://openalex.org/W4253985021","https://openalex.org/W4289821408"],"related_works":["https://openalex.org/W2139520010","https://openalex.org/W2138923007","https://openalex.org/W2019115495","https://openalex.org/W3208292001","https://openalex.org/W2278056556","https://openalex.org/W1996246102","https://openalex.org/W2427540483","https://openalex.org/W2171413266","https://openalex.org/W1998850567","https://openalex.org/W4313477054"],"abstract_inverted_index":{"Time":[0],"interleaving":[1,28,105],"(TI)":[2],"is":[3,25,63,82,96],"an":[4],"effective":[5],"approach":[6],"to":[7,65,132,139],"higher":[8],"speed":[9],"conversion":[10],"of":[11,42,104,113],"current-steering":[12],"digital-to-analog":[13],"converters":[14],"(DACs).":[15],"However,":[16],"achieving":[17,86,128],"high":[18],"linearity":[19],"performance":[20],"for":[21,54],"these":[22],"TI":[23],"DACs":[24],"challenging":[26],"during":[27],"synchronization,":[29],"output":[30],"current":[31,68,91],"summation,":[32],"and":[33,78,107,135],"parasitic":[34,102],"capacitance":[35,103],"control.":[36],"This":[37],"article":[38],"exploits":[39],"the":[40,67,72,101,109,114,125,140],"design":[41],"a":[43,50,90],"6.0-GS/s":[44],"14-bit":[45],"two-channel":[46],"time-interleaved":[47],"DAC":[48,116],"in":[49,71],"65-nm":[51],"CMOS":[52],"process":[53],"communication":[55],"systems.":[56],"A":[57,74],"novel":[58],"asymmetric":[59],"current-tree":[60],"summation":[61,69],"network":[62],"proposed":[64,97,126],"reduce":[66],"nonlinearity":[70],"DAC.":[73],"differential":[75],"clock":[76],"phase":[77],"duty-cycle":[79],"calibration":[80],"scheme":[81,95],"also":[83],"adopted":[84],"while":[85],"low":[87],"complexity.":[88],"Furthermore,":[89],"source":[92],"layout":[93],"optimization":[94],"that":[98],"significantly":[99],"reduces":[100],"switches":[106],"improves":[108],"linearity.":[110],"Measurement":[111],"results":[112],"fabricated":[115],"show":[117],"6\u201320-dB":[118],"spurious-free":[119],"dynamic":[120],"range":[121],"(SFDR)":[122],"improvement":[123],"with":[124],"techniques,":[127],">60-dB":[129],"SFDR":[130,137],"up":[131,138],"1355":[133],"MHz":[134],">50-dB":[136],"Nyquist.":[141]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":7}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
