{"id":"https://openalex.org/W4213166502","doi":"https://doi.org/10.1109/tvlsi.2022.3141326","title":"SoCCom: Automated Synthesis of System-on-Chip Architectures","display_name":"SoCCom: Automated Synthesis of System-on-Chip Architectures","publication_year":2022,"publication_date":"2022-02-16","ids":{"openalex":"https://openalex.org/W4213166502","doi":"https://doi.org/10.1109/tvlsi.2022.3141326"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2022.3141326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2022.3141326","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003543231","display_name":"Atul Prasad Deb Nath","orcid":"https://orcid.org/0000-0002-0050-8379"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Atul Prasad Deb Nath","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":"https://orcid.org/0000-0002-0050-8379","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067367864","display_name":"Kshitij Raj","orcid":"https://orcid.org/0000-0001-9160-5838"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kshitij Raj","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039442844","display_name":"Swarup Bhunia","orcid":"https://orcid.org/0000-0001-6082-6961"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swarup Bhunia","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":"https://orcid.org/0000-0001-6082-6961","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068991400","display_name":"Sandip Ray","orcid":"https://orcid.org/0000-0002-8671-5052"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sandip Ray","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":"https://orcid.org/0000-0002-8671-5052","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":1.2166,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.76139767,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"30","issue":"4","first_page":"449","last_page":"462"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/notation","display_name":"Notation","score":0.6242758631706238},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5119855999946594},{"id":"https://openalex.org/keywords/standardization","display_name":"Standardization","score":0.4731028079986572},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.43709269165992737},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.407239705324173},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3535723090171814},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3268970847129822},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3238489627838135},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.189986914396286},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.13188499212265015},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12350419163703918}],"concepts":[{"id":"https://openalex.org/C45357846","wikidata":"https://www.wikidata.org/wiki/Q2001982","display_name":"Notation","level":2,"score":0.6242758631706238},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5119855999946594},{"id":"https://openalex.org/C188087704","wikidata":"https://www.wikidata.org/wiki/Q369577","display_name":"Standardization","level":2,"score":0.4731028079986572},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.43709269165992737},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.407239705324173},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3535723090171814},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3268970847129822},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3238489627838135},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.189986914396286},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.13188499212265015},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12350419163703918}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2022.3141326","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2022.3141326","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1976955200","https://openalex.org/W1979527452","https://openalex.org/W1990799158","https://openalex.org/W2135211381","https://openalex.org/W2147657366","https://openalex.org/W2151925011","https://openalex.org/W2157225945","https://openalex.org/W2213297816","https://openalex.org/W2403062295","https://openalex.org/W2413263386","https://openalex.org/W2464661970","https://openalex.org/W2581963379","https://openalex.org/W2909562835","https://openalex.org/W2916672784","https://openalex.org/W3009202315","https://openalex.org/W3140077234","https://openalex.org/W3209801326","https://openalex.org/W3211409743","https://openalex.org/W4234833047","https://openalex.org/W4241490134","https://openalex.org/W4241572510","https://openalex.org/W4300101217","https://openalex.org/W6987020231"],"related_works":["https://openalex.org/W2074074927","https://openalex.org/W2461970972","https://openalex.org/W2364921833","https://openalex.org/W2388030554","https://openalex.org/W2302028273","https://openalex.org/W1525643724","https://openalex.org/W2166247150","https://openalex.org/W2067938758","https://openalex.org/W2090686886","https://openalex.org/W2080109731"],"abstract_inverted_index":{"We":[0,16],"present":[1],"CAD":[2],"framework":[3],"and":[4,20,28,52,65,69,77,99],"EDA":[5],"tool,$\\mathrm{S{\\scriptstyle":[6],"O}CC{\\scriptstyle":[7,31,82],"OM}}$,":[8],"for":[9],"automated":[10,25],"synthesis":[11],"of":[12,34,38,47,58,71,85,94,96],"optimized":[13,39],"SoC":[14,97],"architectures.":[15],"delineate":[17],"a":[18,35],"disciplined":[19],"streamlined":[21],"methodology":[22],"to":[23],"enable":[24],"IP":[26],"integration":[27],"design":[29],"optimization.$\\mathrm{S{\\scriptstyle":[30],"OM}}$supports":[32],"generation":[33],"wide":[36],"variety":[37],"SoCs":[40],"by:":[41],"1)":[42],"automating":[43],"the":[44],"entire":[45],"process":[46],"intellectual":[48],"property":[49],"(IP)":[50],"standardization":[51],"integration;":[53],"2)":[54],"allowing":[55],"configurable":[56],"assembly":[57],"complex,":[59],"scalable":[60],"systems":[61],"with":[62],"application-specific":[63],"subsystems;":[64],"3)":[66],"enabling":[67],"optimization":[68],"evaluation":[70],"generated":[72],"designs":[73],"based":[74],"on":[75],"area":[76],"power":[78],"constraints.":[79],"Applications":[80],"of$\\mathrm{S{\\scriptstyle":[81],"OM}}$include":[83],"development":[84],"heterogeneous,":[86],"domain-specific":[87],"SoCs,":[88],"rapid":[89],"register-transfer":[90],"level":[91],"(RTL)":[92],"prototyping":[93],"wide-varieties":[95],"benchmarks,":[98],"many":[100],"others.":[101]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2022,"cited_by_count":2}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}