{"id":"https://openalex.org/W4206632414","doi":"https://doi.org/10.1109/tvlsi.2021.3140206","title":"An 8.55\u201317.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs<sub>rms</sub> Jitter and Fast Frequency Hopping","display_name":"An 8.55\u201317.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs<sub>rms</sub> Jitter and Fast Frequency Hopping","publication_year":2022,"publication_date":"2022-01-13","ids":{"openalex":"https://openalex.org/W4206632414","doi":"https://doi.org/10.1109/tvlsi.2021.3140206"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2021.3140206","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3140206","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061907702","display_name":"Jinhai Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jinhai Xiao","raw_affiliation_strings":["Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020794809","display_name":"Ning Liang","orcid":"https://orcid.org/0000-0003-4201-9220"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ning Liang","raw_affiliation_strings":["Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075122303","display_name":"Bingwen Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bingwen Chen","raw_affiliation_strings":["Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087052960","display_name":"Maliang Liu","orcid":"https://orcid.org/0000-0003-3181-3277"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Maliang Liu","raw_affiliation_strings":["Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"affiliations":[{"raw_affiliation_string":"Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5061907702"],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":1.0065,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.73654222,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"30","issue":"3","first_page":"267","last_page":"276"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7416036128997803},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.6853500604629517},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.659398078918457},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.6384384632110596},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6328586935997009},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.5324360728263855},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.4823736250400543},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.46944093704223633},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4300239384174347},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.42589715123176575},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4024549722671509},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.35199686884880066},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.34970512986183167},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20421838760375977},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.17443624138832092},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.15992659330368042},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1114102303981781}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7416036128997803},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.6853500604629517},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.659398078918457},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.6384384632110596},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6328586935997009},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.5324360728263855},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.4823736250400543},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.46944093704223633},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4300239384174347},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.42589715123176575},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4024549722671509},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35199686884880066},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.34970512986183167},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20421838760375977},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.17443624138832092},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.15992659330368042},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1114102303981781}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2021.3140206","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3140206","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6499999761581421}],"awards":[{"id":"https://openalex.org/G1296667907","display_name":null,"funder_award_id":"62090043","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2320218852","display_name":null,"funder_award_id":"62021004","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4107764394","display_name":null,"funder_award_id":"61874082","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5038432849","display_name":null,"funder_award_id":"61834004","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7010476974","display_name":null,"funder_award_id":"61625403","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1975256196","https://openalex.org/W1994184480","https://openalex.org/W2084270034","https://openalex.org/W2097406868","https://openalex.org/W2130515175","https://openalex.org/W2152259556","https://openalex.org/W2169376357","https://openalex.org/W2172850778","https://openalex.org/W2173725224","https://openalex.org/W2289520113","https://openalex.org/W2342426112","https://openalex.org/W2346049708","https://openalex.org/W2559073178","https://openalex.org/W2565866967","https://openalex.org/W2585026918","https://openalex.org/W2744067478","https://openalex.org/W2744098360","https://openalex.org/W2758621295","https://openalex.org/W2789364534","https://openalex.org/W2790703790","https://openalex.org/W2790721690","https://openalex.org/W2791440917","https://openalex.org/W2791868503","https://openalex.org/W2792205995","https://openalex.org/W2899298050","https://openalex.org/W2904025646","https://openalex.org/W2908118300","https://openalex.org/W2918842581","https://openalex.org/W2921046765","https://openalex.org/W2921338194","https://openalex.org/W2921945517","https://openalex.org/W2944283480","https://openalex.org/W2962846423","https://openalex.org/W3004354595"],"related_works":["https://openalex.org/W2371029054","https://openalex.org/W2370071821","https://openalex.org/W2093119242","https://openalex.org/W2769992427","https://openalex.org/W2394106628","https://openalex.org/W2350996794","https://openalex.org/W2088877925","https://openalex.org/W2384857702","https://openalex.org/W2367423162","https://openalex.org/W2178871507"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"a":[3,106,120,127,131,145],"phase-locked":[4],"loop":[5,52],"(PLL)":[6],"based":[7],"on":[8],"the":[9,17,44,50,100],"direct":[10],"digital":[11],"synthesis":[12],"(DDS)/digital-to-analog":[13],"converter":[14],"(DAC)":[15],"and":[16,31,170],"double-edge":[18],"zero-crossing":[19],"sampling":[20],"phase":[21,45,116],"detector":[22],"(DS-PD)":[23],"for":[24,177],"frequency-modulated":[25],"continuous-wave":[26],"(FMCW)":[27],"radar.":[28],"Its":[29],"DS-PD":[30],"frequency":[32,65,173],"divider":[33],"are":[34],"combined":[35],"to":[36,58,75],"achieve":[37],"refined":[38],"time":[39],"resolution":[40],"while":[41,62,99],"effectively":[42,157],"expanding":[43],"lock":[46],"range,":[47],"thus":[48],"eliminating":[49],"frequency-locked":[51],"(FLL).":[53],"The":[54,81,113,138,154],"DDS/DAC":[55,101],"is":[56,73,123,141,152],"used":[57],"generate":[59],"FMCW":[60,178],"signals":[61],"achieving":[63],"fast":[64,159],"hopping.":[66],"A":[67],"differential":[68],"eight":[69],"switching":[70],"current":[71],"unit":[72],"proposed":[74],"implement":[76],"an":[77],"ultrahigh-speed":[78],"time-interleaved":[79],"DAC.":[80],"8.55\u201317.11-GHz":[82],"PLL":[83,156],"prototype,":[84],"fabricated":[85],"in":[86],"65-nm":[87],"CMOS,":[88],"consumes":[89,102],"10.11":[90],"mW":[91,104],"with":[92,105,130],"0.29-mm":[93],"<sup":[94,108],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[95,109,163],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[96,110],"active":[97,111],"area,":[98],"12.0":[103],"0.16-mm":[107],"area.":[112],"measured":[114],"in-band":[115],"noise":[117],"(PN)":[118],"at":[119,126],"17.11-GHz":[121],"output":[122],"\u2212120.2":[124],"dBc/Hz":[125],"1-MHz":[128],"offset":[129],"root-mean-square":[132],"(rms)":[133],"jitter":[134],"of":[135,149],"51.7":[136],"fs.":[137],"reference":[139],"spur":[140],"<\u221251":[142],"dBc.":[143],"Finally,":[144],"figure-of-merit":[146],"(FoM)":[147],"value":[148],"\u2212255.7":[150],"dB":[151],"obtained.":[153],"prototype":[155],"generates":[158],"(500":[160],"MHz/":[161],"<inline-formula":[162],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[164],"<tex-math":[165],"notation=\"LaTeX\">$3.6~\\mu":[166],"\\text{s}$":[167],"</tex-math></inline-formula>":[168],")":[169],"precise":[171],"(105-kHzrms":[172],"error)":[174],"triangular":[175],"chirps":[176],"radar":[179],"applications.":[180]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}