{"id":"https://openalex.org/W3204115212","doi":"https://doi.org/10.1109/tvlsi.2021.3109560","title":"Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative Examples","display_name":"Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative Examples","publication_year":2021,"publication_date":"2021-09-23","ids":{"openalex":"https://openalex.org/W3204115212","doi":"https://doi.org/10.1109/tvlsi.2021.3109560","mag":"3204115212"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2021.3109560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3109560","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006285592","display_name":"Mohamed B. Elamien","orcid":"https://orcid.org/0000-0002-6528-0010"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohamed B. Elamien","raw_affiliation_strings":["Department of Electrical and Software Engineering, University of Calgary, Calgary, Canada"],"raw_orcid":"https://orcid.org/0000-0002-6528-0010","affiliations":[{"raw_affiliation_string":"Department of Electrical and Software Engineering, University of Calgary, Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014136577","display_name":"Brent Maundy","orcid":"https://orcid.org/0000-0002-3924-2897"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Brent J. Maundy","raw_affiliation_strings":["Department of Electrical and Software Engineering, University of Calgary, Calgary, Canada"],"raw_orcid":"https://orcid.org/0000-0002-3924-2897","affiliations":[{"raw_affiliation_string":"Department of Electrical and Software Engineering, University of Calgary, Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025866057","display_name":"Leonid Belostotski","orcid":"https://orcid.org/0000-0002-5228-6907"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Leonid Belostotski","raw_affiliation_strings":["Department of Electrical and Software Engineering, University of Calgary, Calgary, Canada"],"raw_orcid":"https://orcid.org/0000-0002-5228-6907","affiliations":[{"raw_affiliation_string":"Department of Electrical and Software Engineering, University of Calgary, Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039814573","display_name":"Ahmed S. Elwakil","orcid":"https://orcid.org/0000-0002-3972-5434"},"institutions":[{"id":"https://openalex.org/I29891158","display_name":"University of Sharjah","ror":"https://ror.org/00engpz63","country_code":"AE","type":"education","lineage":["https://openalex.org/I29891158"]}],"countries":["AE"],"is_corresponding":false,"raw_author_name":"Ahmed S. Elwakil","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, United Arab Emirates"],"raw_orcid":"https://orcid.org/0000-0002-3972-5434","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, United Arab Emirates","institution_ids":["https://openalex.org/I29891158"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0983,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.42724902,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"29","issue":"11","first_page":"1850","last_page":"1860"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5611386895179749},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.5523192286491394},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5388455390930176},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.507845938205719},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4954921007156372},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.49042055010795593},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.41927221417427063},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35605692863464355},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32462313771247864},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23800736665725708},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20655235648155212}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5611386895179749},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.5523192286491394},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5388455390930176},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.507845938205719},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4954921007156372},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.49042055010795593},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.41927221417427063},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35605692863464355},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32462313771247864},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23800736665725708},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20655235648155212},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2021.3109560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3109560","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","score":0.699999988079071,"display_name":"Quality Education"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320994","display_name":"Canada Research Chairs","ror":"https://ror.org/0517h6h17"},{"id":"https://openalex.org/F4320325651","display_name":"Alberta Innovates","ror":null},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":45,"referenced_works":["https://openalex.org/W1566916904","https://openalex.org/W1865663301","https://openalex.org/W1996371457","https://openalex.org/W2017013043","https://openalex.org/W2032735355","https://openalex.org/W2048514579","https://openalex.org/W2075545359","https://openalex.org/W2075867689","https://openalex.org/W2088389697","https://openalex.org/W2090709385","https://openalex.org/W2108732866","https://openalex.org/W2126442888","https://openalex.org/W2133277273","https://openalex.org/W2136284655","https://openalex.org/W2141776905","https://openalex.org/W2161359911","https://openalex.org/W2162204589","https://openalex.org/W2167014994","https://openalex.org/W2291880745","https://openalex.org/W2425442423","https://openalex.org/W2618546898","https://openalex.org/W2789306143","https://openalex.org/W2790986675","https://openalex.org/W2796863645","https://openalex.org/W2803174758","https://openalex.org/W2886655347","https://openalex.org/W2893313719","https://openalex.org/W2899469393","https://openalex.org/W2902903140","https://openalex.org/W2912648094","https://openalex.org/W2914329358","https://openalex.org/W2942072122","https://openalex.org/W2942865408","https://openalex.org/W2982411542","https://openalex.org/W2982435733","https://openalex.org/W2995735067","https://openalex.org/W3002268885","https://openalex.org/W3014415941","https://openalex.org/W3047369557","https://openalex.org/W3048081910","https://openalex.org/W3088813634","https://openalex.org/W3203011645","https://openalex.org/W4398233154","https://openalex.org/W6684066572","https://openalex.org/W6769907493"],"related_works":["https://openalex.org/W1905216755","https://openalex.org/W2104218257","https://openalex.org/W2375192119","https://openalex.org/W2122222688","https://openalex.org/W1933057227","https://openalex.org/W2965949386","https://openalex.org/W3038003875","https://openalex.org/W2991387620","https://openalex.org/W4303491838","https://openalex.org/W4213259602"],"abstract_inverted_index":{"In":[0,110],"this":[1,76,108],"article,":[2],"a":[3,89,117,123],"synthesis":[4,77,142],"methodology":[5,13,78],"for":[6,23,46],"analog":[7,25,64],"circuit":[8],"design":[9,114],"is":[10],"presented.":[11],"This":[12,92],"utilizes":[14],"symbolic":[15,50],"math":[16,51],"tools":[17],"to":[18,58,95,137],"systematically":[19],"and":[20,66,73,82,97,122,132,139],"exhaustively":[21],"search":[22],"candidate":[24],"circuits":[26,65],"avoiding":[27],"tedious":[28],"manual":[29],"work.":[30],"The":[31],"two-port":[32],"network":[33],"matrix":[34],"representation":[35],"of":[36,62,71,101,105,116,119,125],"active":[37],"devices,":[38],"such":[39],"as":[40],"MOS":[41],"transistors,":[42],"paves":[43],"the":[44,60,69,102,141],"way":[45],"efficiently":[47],"using":[48],"advanced":[49],"toolboxes":[52],"(e.g.,":[53],"in":[54,107],"MAPLE":[55],"or":[56],"MATLAB)":[57],"automate":[59],"generation":[61],"new":[63,79],"further":[67],"investigate":[68],"effects":[70],"nonidealities":[72],"parasitics.":[74],"Using":[75],"amplifiers,":[80],"filters,":[81],"oscillators":[83,127],"can":[84],"be":[85],"obtained":[86],"starting":[87],"from":[88],"predefined":[90],"structure.":[91],"article":[93],"aims":[94],"motivate":[96],"provide":[98],"an":[99],"overview":[100],"current":[103],"status":[104],"research":[106],"area.":[109],"addition,":[111],"two":[112],"detailed":[113],"examples":[115],"family":[118,124],"differential":[120,126],"filters":[121],"along":[128],"with":[129],"their":[130],"simulations":[131],"measurement":[133],"results":[134],"are":[135],"provided":[136],"illustrate":[138],"verify":[140],"methodology.":[143]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}