{"id":"https://openalex.org/W3196467229","doi":"https://doi.org/10.1109/tvlsi.2021.3107404","title":"Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis","display_name":"Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis","publication_year":2021,"publication_date":"2021-09-03","ids":{"openalex":"https://openalex.org/W3196467229","doi":"https://doi.org/10.1109/tvlsi.2021.3107404","mag":"3196467229"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2021.3107404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3107404","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059244271","display_name":"Zhenxin Zhao","orcid":"https://orcid.org/0000-0003-4902-353X"},"institutions":[{"id":"https://openalex.org/I130438778","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03","country_code":"CA","type":"education","lineage":["https://openalex.org/I130438778"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Zhenxin Zhao","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John\u2019s, NL, Canada","Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John's, NL, Canada"],"raw_orcid":"https://orcid.org/0000-0003-4902-353X","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John\u2019s, NL, Canada","institution_ids":["https://openalex.org/I130438778"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John's, NL, Canada","institution_ids":["https://openalex.org/I130438778"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100705837","display_name":"Lihong Zhang","orcid":"https://orcid.org/0000-0003-2946-8072"},"institutions":[{"id":"https://openalex.org/I130438778","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03","country_code":"CA","type":"education","lineage":["https://openalex.org/I130438778"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Lihong Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John\u2019s, NL, Canada","Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John's, NL, Canada"],"raw_orcid":"https://orcid.org/0000-0003-2946-8072","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John\u2019s, NL, Canada","institution_ids":["https://openalex.org/I130438778"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Faculty of Engineering and Applied Science, Memorial University of Newfoundland, St. John's, NL, Canada","institution_ids":["https://openalex.org/I130438778"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130438778"],"apc_list":null,"apc_paid":null,"fwci":1.7702,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.84863849,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"29","issue":"11","first_page":"1824","last_page":"1837"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9312558174133301},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6857314109802246},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.6134335398674011},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4958229959011078},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4631134569644928},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45357075333595276},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.44788238406181335},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4267512857913971},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4061112403869629},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3664402961730957},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35659414529800415},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18491652607917786},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15681210160255432},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14078843593597412},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11442697048187256}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9312558174133301},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6857314109802246},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.6134335398674011},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4958229959011078},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4631134569644928},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45357075333595276},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.44788238406181335},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4267512857913971},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4061112403869629},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3664402961730957},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35659414529800415},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18491652607917786},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15681210160255432},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14078843593597412},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11442697048187256},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2021.3107404","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3107404","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320319952","display_name":"Canada Foundation for Innovation","ror":"https://ror.org/000az4664"},{"id":"https://openalex.org/F4320323319","display_name":"Memorial University of Newfoundland","ror":"https://ror.org/04haebc03"},{"id":"https://openalex.org/F4320328585","display_name":"Newfoundland and Labrador","ror":null},{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1528686882","https://openalex.org/W1719971006","https://openalex.org/W1727049600","https://openalex.org/W1981681015","https://openalex.org/W2074046446","https://openalex.org/W2080464715","https://openalex.org/W2109755562","https://openalex.org/W2110073735","https://openalex.org/W2117564662","https://openalex.org/W2118158907","https://openalex.org/W2122156639","https://openalex.org/W2155811837","https://openalex.org/W2157873272","https://openalex.org/W2165666706","https://openalex.org/W2291962954","https://openalex.org/W2403278033","https://openalex.org/W2539776105","https://openalex.org/W2555866191","https://openalex.org/W2588897393","https://openalex.org/W2778822537","https://openalex.org/W2795315247","https://openalex.org/W2799971163","https://openalex.org/W2800869073","https://openalex.org/W2905247075","https://openalex.org/W2983257683","https://openalex.org/W3009193187","https://openalex.org/W3089997764","https://openalex.org/W3124031675","https://openalex.org/W4237746091","https://openalex.org/W4242427575","https://openalex.org/W4247282788","https://openalex.org/W4252425434","https://openalex.org/W6677260540","https://openalex.org/W6683185311","https://openalex.org/W6783745106"],"related_works":["https://openalex.org/W4292182797","https://openalex.org/W4285047337","https://openalex.org/W2053072356","https://openalex.org/W2044303612","https://openalex.org/W2532989920","https://openalex.org/W4246262701","https://openalex.org/W2304374807","https://openalex.org/W1491101179","https://openalex.org/W3216447180","https://openalex.org/W2348452903"],"abstract_inverted_index":{"Fast":[0],"and":[1,64,149],"accurate":[2,43,100],"performance":[3,20,28,155],"estimation":[4],"can":[5,24,113],"significantly":[6],"enhance":[7],"the":[8,50,60,74,86,95,99,107,141],"efficiency":[9],"of":[10,49,88,152],"automated":[11],"analog":[12],"circuit":[13,27,36,69,75,96,123],"synthesis.":[14],"This":[15],"article":[16],"presents":[17],"a":[18,68],"novel":[19],"modeling":[21,45,156],"method":[22,40],"that":[23],"efficiently":[25],"estimate":[26],"with":[29,42,85],"ignorable":[30],"model":[31,109,143],"building":[32],"overhead":[33],"for":[34],"variant":[35],"topologies.":[37],"The":[38],"proposed":[39,154],"starts":[41],"transistor":[44,62,102],"by":[46],"taking":[47],"advantage":[48],"advanced":[51],"neural":[52],"network":[53],"(NN)":[54],"fitting":[55],"technique.":[56],"It":[57],"then":[58],"utilizes":[59],"established":[61],"models":[63,103],"topology":[65],"information":[66],"from":[67,94],"netlist":[70],"to":[71,117,121],"precisely":[72],"discover":[73],"dc":[76,133],"operating":[77,134],"point.":[78],"Specialized":[79],"deterministic":[80,132],"schemes":[81,137],"have":[82],"been":[83],"developed":[84],"aid":[87],"an":[89],"undirected":[90],"bipartite":[91],"graph":[92],"converted":[93],"netlist.":[97],"Moreover,":[98],"NN":[101],"help":[104],"directly":[105],"derive":[106],"small-signal":[108],"parameter":[110],"values,":[111],"which":[112],"be":[114],"further":[115],"applied":[116],"conduct":[118],"symbolic":[119],"analysis":[120],"evaluate":[122],"performances.":[124],"Our":[125],"experimental":[126],"results":[127],"not":[128],"only":[129],"compare":[130],"various":[131],"point":[135],"computation":[136],"but":[138],"also":[139],"demonstrate":[140],"efficient":[142],"development,":[144],"general":[145],"applicability,":[146],"speedy":[147],"execution,":[148],"fair":[150],"prediction":[151],"our":[153],"method.":[157]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":10},{"year":2024,"cited_by_count":9},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}