{"id":"https://openalex.org/W3171505068","doi":"https://doi.org/10.1109/tvlsi.2021.3082760","title":"Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs","display_name":"Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs","publication_year":2021,"publication_date":"2021-06-03","ids":{"openalex":"https://openalex.org/W3171505068","doi":"https://doi.org/10.1109/tvlsi.2021.3082760","mag":"3171505068"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2021.3082760","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3082760","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031531908","display_name":"Yoshisato Yokoyama","orcid":"https://orcid.org/0000-0001-8552-4070"},"institutions":[{"id":"https://openalex.org/I27429435","display_name":"Kyoto Institute of Technology","ror":"https://ror.org/00965ax52","country_code":"JP","type":"education","lineage":["https://openalex.org/I27429435"]},{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshisato Yokoyama","raw_affiliation_strings":["Kyoto Institute of Technology, Kyoto, Japan","Renesas Electronics Corporation, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0001-8552-4070","affiliations":[{"raw_affiliation_string":"Kyoto Institute of Technology, Kyoto, Japan","institution_ids":["https://openalex.org/I27429435"]},{"raw_affiliation_string":"Renesas Electronics Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102538016","display_name":"Yuichiro Ishii","orcid":null},"institutions":[{"id":"https://openalex.org/I4210151210","display_name":"Technical Design (United States)","ror":"https://ror.org/041cwwp58","country_code":"US","type":"company","lineage":["https://openalex.org/I4210151210"]},{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP","US"],"is_corresponding":false,"raw_author_name":"Yuichiro Ishii","raw_affiliation_strings":["Japan Memory Design Program, TSMC Design Technology Japan, Yokohama, Japan","Renesas Electronics Corporation, Tokyo, Japan","Renesas Electronics Corporation,Tokyo,Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Japan Memory Design Program, TSMC Design Technology Japan, Yokohama, Japan","institution_ids":["https://openalex.org/I4210151210"]},{"raw_affiliation_string":"Renesas Electronics Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]},{"raw_affiliation_string":"Renesas Electronics Corporation,Tokyo,Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047952713","display_name":"Koji Nii","orcid":"https://orcid.org/0000-0002-9986-5308"},"institutions":[{"id":"https://openalex.org/I27429435","display_name":"Kyoto Institute of Technology","ror":"https://ror.org/00965ax52","country_code":"JP","type":"education","lineage":["https://openalex.org/I27429435"]},{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Koji Nii","raw_affiliation_strings":["Kyoto Institute of Technology, Kyoto, Japan","Renesas Electronics Corporation, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Kyoto Institute of Technology, Kyoto, Japan","institution_ids":["https://openalex.org/I27429435"]},{"raw_affiliation_string":"Renesas Electronics Corporation, Tokyo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049656449","display_name":"Kazutoshi Kobayashi","orcid":"https://orcid.org/0000-0002-7139-7274"},"institutions":[{"id":"https://openalex.org/I27429435","display_name":"Kyoto Institute of Technology","ror":"https://ror.org/00965ax52","country_code":"JP","type":"education","lineage":["https://openalex.org/I27429435"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazutoshi Kobayashi","raw_affiliation_strings":["Kyoto Institute of Technology, Kyoto, Japan","Kyoto Institute of Technology, Kyoto, JAPAN"],"raw_orcid":"https://orcid.org/0000-0002-7139-7274","affiliations":[{"raw_affiliation_string":"Kyoto Institute of Technology, Kyoto, Japan","institution_ids":["https://openalex.org/I27429435"]},{"raw_affiliation_string":"Kyoto Institute of Technology, Kyoto, JAPAN","institution_ids":["https://openalex.org/I27429435"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3051,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.5590503,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"29","issue":"7","first_page":"1495","last_page":"1499"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/megabit","display_name":"Megabit","score":0.8131365776062012},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7028243541717529},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.6617777347564697},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6477982401847839},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4309771656990051},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.41533762216567993},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4150086045265198},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41102293133735657},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3776005208492279},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35384148359298706},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32002532482147217},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1752600073814392},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15842923521995544}],"concepts":[{"id":"https://openalex.org/C185177783","wikidata":"https://www.wikidata.org/wiki/Q3332814","display_name":"Megabit","level":2,"score":0.8131365776062012},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7028243541717529},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.6617777347564697},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6477982401847839},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4309771656990051},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.41533762216567993},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4150086045265198},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41102293133735657},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3776005208492279},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35384148359298706},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32002532482147217},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1752600073814392},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15842923521995544},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2021.3082760","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3082760","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6100000143051147,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1923374043","https://openalex.org/W2002612140","https://openalex.org/W2024601697","https://openalex.org/W2039689952","https://openalex.org/W2049520384","https://openalex.org/W2057540030","https://openalex.org/W2091808869","https://openalex.org/W2100827158","https://openalex.org/W2117139377","https://openalex.org/W2118009298","https://openalex.org/W2148866533","https://openalex.org/W2150068225","https://openalex.org/W2155488321","https://openalex.org/W2243795914","https://openalex.org/W2328407804","https://openalex.org/W2564315205","https://openalex.org/W6665016880","https://openalex.org/W6681960279"],"related_works":["https://openalex.org/W2315752188","https://openalex.org/W2116914742","https://openalex.org/W2056087990","https://openalex.org/W3148563749","https://openalex.org/W2102143584","https://openalex.org/W1580783998","https://openalex.org/W3022395656","https://openalex.org/W2371858336","https://openalex.org/W185967396","https://openalex.org/W1637603355"],"abstract_inverted_index":{"Embedded":[0],"static":[1],"random":[2],"access":[3],"memories":[4],"(SRAMs)":[5],"with":[6,91,129],"cost-effective":[7],"test":[8,20,119,134,142],"screening":[9],"circuitry":[10],"are":[11,104],"demonstrated":[12],"for":[13],"low-power":[14,109],"microcontroller":[15],"units":[16],"(MCUs).":[17],"The":[18,132],"probing":[19],"step":[21],"at":[22,46],"the":[23,38,117,141],"low":[24],"temperature":[25,48],"(LT)":[26],"of":[27,94,140],"-40":[28],"\u00b0C":[29],"is":[30,44,53],"obviated":[31],"by":[32],"imitating":[33],"pseudo-LT":[34],"(PLT)":[35],"conditions":[36,123],"in":[37],"package":[39],"test,":[40],"where":[41],"a":[42],"sample":[43],"measured":[45],"room":[47],"(RT).":[49],"Monte":[50],"Carlo":[51],"simulation":[52],"carried":[54],"out":[55,126],"considering":[56],"local":[57],"V":[58,78],"<sub":[59,79],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[60,80],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">t</sub>":[61],"variations":[62],"as":[63,65],"well":[64],"contact":[66],"soft":[67],"open":[68],"failure":[69],"(high":[70],"resistance),":[71],"confirming":[72],"good":[73],"minimum":[74],"operating":[75],"voltage":[76],"(":[77],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">min</sub>":[81],")":[82],"correlation":[83],"between":[84],"LT":[85,122,127],"and":[86,99,106,124],"PLT":[87],"conditions.":[88],"Test":[89],"chips":[90],"two":[92],"types":[93],"4-Mbit":[95],"single-port":[96],"SRAM":[97,102],"macros":[98],"1-Mbit":[100],"dual-port":[101],"macro":[103],"designed":[105],"fabricated":[107],"using":[108],"40-nm":[110],"CMOS":[111],"technology.":[112],"Measurement":[113],"results":[114],"demonstrate":[115],"that":[116],"proposed":[118,133],"method":[120,135],"reproduces":[121],"screens":[125],"failures":[128],"less":[130],"overscreening.":[131],"eliminates":[136],"1/3":[137],"or":[138],"more":[139],"costs.":[143]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
