{"id":"https://openalex.org/W3142587068","doi":"https://doi.org/10.1109/tvlsi.2021.3068450","title":"Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation","display_name":"Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation","publication_year":2021,"publication_date":"2021-04-02","ids":{"openalex":"https://openalex.org/W3142587068","doi":"https://doi.org/10.1109/tvlsi.2021.3068450","mag":"3142587068"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2021.3068450","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3068450","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/11585/859706","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033037232","display_name":"Pierpaolo Palestri","orcid":"https://orcid.org/0000-0002-1672-1166"},"institutions":[{"id":"https://openalex.org/I129043915","display_name":"University of Udine","ror":"https://ror.org/05ht0mh31","country_code":"IT","type":"education","lineage":["https://openalex.org/I129043915"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Pierpaolo Palestri","raw_affiliation_strings":["DPIA, University of Udine, Udine, Italy"],"raw_orcid":"https://orcid.org/0000-0002-1672-1166","affiliations":[{"raw_affiliation_string":"DPIA, University of Udine, Udine, Italy","institution_ids":["https://openalex.org/I129043915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033967053","display_name":"Ahmed Elnaqib","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Ahmed Elnaqib","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091717988","display_name":"Davide Menin","orcid":"https://orcid.org/0000-0002-8859-1073"},"institutions":[{"id":"https://openalex.org/I129043915","display_name":"University of Udine","ror":"https://ror.org/05ht0mh31","country_code":"IT","type":"education","lineage":["https://openalex.org/I129043915"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Menin","raw_affiliation_strings":["DPIA, University of Udine, Udine, Italy"],"raw_orcid":"https://orcid.org/0000-0002-8859-1073","affiliations":[{"raw_affiliation_string":"DPIA, University of Udine, Udine, Italy","institution_ids":["https://openalex.org/I129043915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078811059","display_name":"Klaid Shyti","orcid":"https://orcid.org/0000-0002-0189-8639"},"institutions":[{"id":"https://openalex.org/I129043915","display_name":"University of Udine","ror":"https://ror.org/05ht0mh31","country_code":"IT","type":"education","lineage":["https://openalex.org/I129043915"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Klaid Shyti","raw_affiliation_strings":["DPIA, University of Udine, Udine, Italy"],"raw_orcid":"https://orcid.org/0000-0002-0189-8639","affiliations":[{"raw_affiliation_string":"DPIA, University of Udine, Udine, Italy","institution_ids":["https://openalex.org/I129043915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004318385","display_name":"Francesco Brandonisio","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Francesco Brandonisio","raw_affiliation_strings":["Infineon Technologies Villach (Austria), Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies Villach (Austria), Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060798247","display_name":"Andrea Bandiziol","orcid":"https://orcid.org/0000-0002-7950-0416"},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Andrea Bandiziol","raw_affiliation_strings":["Infineon Technologies Villach (Austria), Villach, Austria"],"raw_orcid":"https://orcid.org/0000-0002-7950-0416","affiliations":[{"raw_affiliation_string":"Infineon Technologies Villach (Austria), Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023905268","display_name":"Davide Rossi","orcid":"https://orcid.org/0000-0002-0651-5393"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Rossi","raw_affiliation_strings":["University of Bologna, Bologna, Italy"],"raw_orcid":"https://orcid.org/0000-0002-0651-5393","affiliations":[{"raw_affiliation_string":"University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011833987","display_name":"Roberto Nonis","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Roberto Nonis","raw_affiliation_strings":["Infineon Technologies Villach (Austria), Villach, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies Villach (Austria), Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3934,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.58170712,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"29","issue":"7","first_page":"1392","last_page":"1401"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.937595009803772},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5962311029434204},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.5790903568267822},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.5770503878593445},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5545036792755127},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5436408519744873},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5139490962028503},{"id":"https://openalex.org/keywords/clock-recovery","display_name":"Clock recovery","score":0.4711246192455292},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.46237799525260925},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42376843094825745},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2753939926624298},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.22091606259346008},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18942761421203613},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16313883662223816},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13903018832206726}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.937595009803772},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5962311029434204},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.5790903568267822},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.5770503878593445},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5545036792755127},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5436408519744873},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5139490962028503},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.4711246192455292},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.46237799525260925},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42376843094825745},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2753939926624298},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.22091606259346008},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18942761421203613},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16313883662223816},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13903018832206726},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tvlsi.2021.3068450","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2021.3068450","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},{"id":"pmh:oai:air.uniud.it:11390/1206439","is_oa":false,"landing_page_url":"http://hdl.handle.net/11390/1206439","pdf_url":null,"source":{"id":"https://openalex.org/S4306401163","display_name":"Institutional Research Information System (University of Udine)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I129043915","host_organization_name":"University of Udine","host_organization_lineage":["https://openalex.org/I129043915"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:cris.unibo.it:11585/859706","is_oa":true,"landing_page_url":"http://hdl.handle.net/11585/859706","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:iris.unimore.it:11380/1328094","is_oa":true,"landing_page_url":"https://hdl.handle.net/11380/1328094","pdf_url":null,"source":{"id":"https://openalex.org/S4306400718","display_name":"IRIS UNIMORE (University of Modena and Reggio Emilia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I122346577","host_organization_name":"University of Modena and Reggio Emilia","host_organization_lineage":["https://openalex.org/I122346577"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:cris.unibo.it:11585/859706","is_oa":true,"landing_page_url":"http://hdl.handle.net/11585/859706","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W146784561","https://openalex.org/W1775840686","https://openalex.org/W2031380370","https://openalex.org/W2089328455","https://openalex.org/W2096729557","https://openalex.org/W2107208989","https://openalex.org/W2112489816","https://openalex.org/W2123892792","https://openalex.org/W2132897890","https://openalex.org/W2134104208","https://openalex.org/W2141028418","https://openalex.org/W2144581882","https://openalex.org/W2151100180","https://openalex.org/W2153123737","https://openalex.org/W2154332266","https://openalex.org/W2172802475","https://openalex.org/W2591899075","https://openalex.org/W2790928636","https://openalex.org/W2800532110","https://openalex.org/W2809876975","https://openalex.org/W3002466325","https://openalex.org/W4246804698","https://openalex.org/W6734471224","https://openalex.org/W6749397863"],"related_works":["https://openalex.org/W2139484866","https://openalex.org/W2035322460","https://openalex.org/W1574257586","https://openalex.org/W2908219865","https://openalex.org/W2295601265","https://openalex.org/W2148370333","https://openalex.org/W2936029881","https://openalex.org/W2096085680","https://openalex.org/W1565428738","https://openalex.org/W2097069023"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"compact":[3],"expressions":[4],"for":[5,141],"the":[6,21,25,33,38,44,50,54,61,72,78,82,85,89,93,97,104,108,112,116,129],"jitter":[7,87],"in":[8],"clock":[9,52,86,142],"and":[10,27,67],"data":[11,66],"recovery":[12],"(CDR)":[13],"circuits":[14],"based":[15],"on":[16,64,88,92],"bang-bang":[17],"phase":[18,22,45],"detector":[19],"including":[20,132],"noise":[23,35,109],"of":[24,41,43,74,84,115,128],"transmitter":[26],"receiver":[28,51],"oscillators":[29,134],"as":[30,32,135,137],"well":[31,136],"quantization":[34],"associated":[36],"with":[37],"finite":[39,113],"number":[40],"phases":[42,114],"interpolator":[46],"(PI)":[47],"that":[48],"align":[49],"to":[53,59,111],"incoming":[55],"data.":[56],"Different":[57],"approaches":[58],"perform":[60],"Early/Late":[62,99],"detection":[63],"deserialized":[65],"edge":[68],"samples":[69],"are":[70,122],"compared:":[71],"use":[73],"majority":[75],"voting":[76],"degrades":[77],"CDR":[79,90,130],"bandwidth,":[80],"increasing":[81],"impact":[83],"jitter;":[91],"other":[94],"hand,":[95],"counting":[96],"single":[98],"occurrences":[100],"does":[101],"not":[102],"degrade":[103],"bandwidth":[105],"but":[106],"increases":[107],"related":[110],"PI.":[117],"The":[118],"proposed":[119],"analytical":[120],"formulas":[121],"validated":[123],"against":[124],"event-driven":[125],"behavioral":[126],"simulations":[127],"system":[131],"free-running":[133],"phase-locked":[138],"loop":[139],"(PLL)":[140],"generation.":[143]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2021-04-13T00:00:00"}