{"id":"https://openalex.org/W3049364631","doi":"https://doi.org/10.1109/tvlsi.2020.3013139","title":"Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping","display_name":"Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping","publication_year":2020,"publication_date":"2020-08-14","ids":{"openalex":"https://openalex.org/W3049364631","doi":"https://doi.org/10.1109/tvlsi.2020.3013139","mag":"3049364631"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2020.3013139","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.3013139","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030255041","display_name":"Even L\u00e5te","orcid":"https://orcid.org/0000-0002-3333-1071"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Even Late","raw_affiliation_strings":["Department of Electronics and Telecommunications, Norges teknisk-naturvitenskapelige universitet, Trondheim, Norway"],"raw_orcid":"https://orcid.org/0000-0002-3333-1071","affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Norges teknisk-naturvitenskapelige universitet, Trondheim, Norway","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055804223","display_name":"Trond Ytterdal","orcid":"https://orcid.org/0000-0002-2109-833X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Trond Ytterdal","raw_affiliation_strings":["Department of Electronics and Telecommunications, Norges teknisk-naturvitenskapelige universitet, Trondheim, Norway"],"raw_orcid":"https://orcid.org/0000-0002-2109-833X","affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Norges teknisk-naturvitenskapelige universitet, Trondheim, Norway","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026627174","display_name":"Snorre Aunet","orcid":"https://orcid.org/0000-0002-6465-8886"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Snorre Aunet","raw_affiliation_strings":["Department of Electronics and Telecommunications, Norges teknisk-naturvitenskapelige universitet, Trondheim, Norway"],"raw_orcid":"https://orcid.org/0000-0002-6465-8886","affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Norges teknisk-naturvitenskapelige universitet, Trondheim, Norway","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030255041"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0732346,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"28","issue":"10","first_page":"2223","last_page":"2227"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.609649658203125},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5655136108398438},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.48639944195747375},{"id":"https://openalex.org/keywords/word","display_name":"Word (group theory)","score":0.4858683943748474},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.44748884439468384},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.42642587423324585},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.41763049364089966},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4040426015853882},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37065932154655457},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3545262813568115},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3353060185909271},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2766071557998657},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23524460196495056},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11260440945625305}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.609649658203125},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5655136108398438},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.48639944195747375},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.4858683943748474},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.44748884439468384},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.42642587423324585},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41763049364089966},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4040426015853882},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37065932154655457},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3545262813568115},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3353060185909271},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2766071557998657},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23524460196495056},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11260440945625305},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2020.3013139","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.3013139","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1968464410","https://openalex.org/W1972799126","https://openalex.org/W2019828391","https://openalex.org/W2119472374","https://openalex.org/W2161573394","https://openalex.org/W2165072326","https://openalex.org/W2344726030","https://openalex.org/W2511964095"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W4378977321","https://openalex.org/W1976168335","https://openalex.org/W4308090481","https://openalex.org/W3211992815","https://openalex.org/W179354024"],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"an":[3,22,87],"approach":[4],"that":[5,83,124],"dynamically":[6],"exploits":[7],"content":[8],"dependencies":[9],"in":[10,55,102,204],"asymmetric":[11,88,104],"memory":[12,26,49,60,105],"cells.":[13],"By":[14],"using":[15,79],"a":[16,56,72,92,194,208],"capacitive,":[17],"logic-value":[18],"majority":[19],"circuit":[20],"and":[21,53,65,75,160,162],"extra":[23],"column":[24],"of":[25,47,95,131,140,177,190,197,212],"cells,":[27],"words":[28,139,175,188],"are":[29],"conditionally":[30],"flipped":[31],"during":[32],"write":[33,74],"operations":[34],"to":[35,86,166],"reach":[36],"the":[37,98,103,125,132,145,149,153,180,202,215],"more":[38],"beneficial":[39],"state":[40],"for":[41,137,152,214],"storage.":[42],"A":[43,119],"1-kb":[44],"SRAM":[45,147],"block":[46],"low-voltage":[48],"cells":[50,61],"was":[51],"implemented":[52,146],"manufactured":[54],"130-nm":[57],"CMOS.":[58],"The":[59],"were":[62],"made":[63],"writable":[64],"read-stable":[66],"at":[67],"low":[68],"supply":[69,93],"voltages":[70],"with":[71,116,207],"single-ended":[73,76],"read":[77],"structure":[78],"six":[80],"multithreshold":[81],"transistors":[82],"give":[84],"rise":[85],"retention":[89,154,205],"power.":[90],"At":[91],"voltage":[94],"350":[96],"mV,":[97],"content-dependent":[99],"leakage":[100],"power":[101,129,155,181,195,206],"cell":[106],"is":[107],"23":[108],"times":[109],"smaller":[110],"when":[111],"storing":[112],"logic":[113,117,159],"\u201c1\u201ds":[114],"compared":[115],"\u201c0\u201ds.":[118],"derived":[120],"statistical":[121],"model":[122],"suggests":[123],"mean,":[126],"wordwise,":[127],"static":[128],"savings":[130],"word-flipping":[133],"scheme":[134],"become":[135],"15.70%":[136],"8-bit":[138],"uniform":[141],"bit":[142],"probability.":[143],"For":[144],"macro,":[148],"mean":[150,210],"improvement":[151,203,211],"is,":[156],"including":[157],"flip":[158],"decoder":[161],"driver":[163],"overheads,":[164],"found":[165],"be":[167],"14.69%.":[168],"In":[169],"boundary":[170],"tests,":[171],"by":[172],"writing":[173,186],"all":[174,187],"full":[176,189],"undesired":[178],"values,":[179],"saving":[182],"becomes":[183],"80.37%,":[184],"while":[185],"desired":[191],"values":[192],"causes":[193],"penalty":[196],"6.14%.":[198],"Measurement":[199],"results":[200],"confirm":[201],"ten-chip":[209],"11.93%":[213],"same":[216],"data":[217],"set.":[218]},"counts_by_year":[],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}