{"id":"https://openalex.org/W3016940091","doi":"https://doi.org/10.1109/tvlsi.2020.2983850","title":"High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR\u2013XNOR Cell","display_name":"High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR\u2013XNOR Cell","publication_year":2020,"publication_date":"2020-04-15","ids":{"openalex":"https://openalex.org/W3016940091","doi":"https://doi.org/10.1109/tvlsi.2020.2983850","mag":"3016940091"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2020.2983850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2983850","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Jyoti Kandpal","orcid":"https://orcid.org/0000-0002-4889-5363"},"institutions":[{"id":"https://openalex.org/I252758333","display_name":"Govind Ballabh Pant University of Agriculture and Technology","ror":"https://ror.org/02msjvh03","country_code":"IN","type":"education","lineage":["https://openalex.org/I252758333"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jyoti Kandpal","raw_affiliation_strings":["Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India"],"raw_orcid":"https://orcid.org/0000-0002-4889-5363","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India","institution_ids":["https://openalex.org/I252758333"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081198287","display_name":"Abhishek Tomar","orcid":"https://orcid.org/0000-0002-1032-547X"},"institutions":[{"id":"https://openalex.org/I252758333","display_name":"Govind Ballabh Pant University of Agriculture and Technology","ror":"https://ror.org/02msjvh03","country_code":"IN","type":"education","lineage":["https://openalex.org/I252758333"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abhishek Tomar","raw_affiliation_strings":["Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India","institution_ids":["https://openalex.org/I252758333"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029643822","display_name":"Mayur Agarwal","orcid":"https://orcid.org/0000-0003-0729-4606"},"institutions":[{"id":"https://openalex.org/I252758333","display_name":"Govind Ballabh Pant University of Agriculture and Technology","ror":"https://ror.org/02msjvh03","country_code":"IN","type":"education","lineage":["https://openalex.org/I252758333"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mayur Agarwal","raw_affiliation_strings":["Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India"],"raw_orcid":"https://orcid.org/0000-0003-0729-4606","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India","institution_ids":["https://openalex.org/I252758333"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085876705","display_name":"Kamal Kumar Sharma","orcid":"https://orcid.org/0000-0002-6294-0829"},"institutions":[{"id":"https://openalex.org/I252758333","display_name":"Govind Ballabh Pant University of Agriculture and Technology","ror":"https://ror.org/02msjvh03","country_code":"IN","type":"education","lineage":["https://openalex.org/I252758333"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. K. Sharma","raw_affiliation_strings":["Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, College of Technology, G. B. Pant University of Agriculture and Technology, Pantnagar, India","institution_ids":["https://openalex.org/I252758333"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I252758333"],"apc_list":{"value":2045,"currency":"USD","value_usd":2045},"apc_paid":null,"fwci":5.9596,"has_fulltext":false,"cited_by_count":129,"citation_normalized_percentile":{"value":0.97179417,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":99,"max":100},"biblio":{"volume":"28","issue":"6","first_page":"1413","last_page":"1422"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.9874122142791748},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8272343277931213},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6610227227210999},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.576275110244751},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5060939192771912},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4924250543117523},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.48882266879081726},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4575258195400238},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4466618299484253},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.4460504949092865},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4445026218891144},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4254814386367798},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34545499086380005},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1928308606147766},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1702137589454651},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1627274453639984},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.11318936944007874},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.0761299729347229}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.9874122142791748},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8272343277931213},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6610227227210999},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.576275110244751},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5060939192771912},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4924250543117523},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.48882266879081726},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4575258195400238},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4466618299484253},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.4460504949092865},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4445026218891144},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4254814386367798},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34545499086380005},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1928308606147766},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1702137589454651},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1627274453639984},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.11318936944007874},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0761299729347229},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2020.2983850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2983850","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322724","display_name":"Ministry of Education, India","ror":"https://ror.org/048xjjh50"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1882870471","https://openalex.org/W1994627436","https://openalex.org/W2007043968","https://openalex.org/W2025315299","https://openalex.org/W2046103068","https://openalex.org/W2067192709","https://openalex.org/W2119985366","https://openalex.org/W2124278579","https://openalex.org/W2131107384","https://openalex.org/W2141849037","https://openalex.org/W2144038159","https://openalex.org/W2147970500","https://openalex.org/W2159229333","https://openalex.org/W2166243422","https://openalex.org/W2507870178","https://openalex.org/W2791867184","https://openalex.org/W2803057706","https://openalex.org/W6638957527"],"related_works":["https://openalex.org/W1913026194","https://openalex.org/W2067192709","https://openalex.org/W1981364906","https://openalex.org/W2151908724","https://openalex.org/W4281638751","https://openalex.org/W2949250270","https://openalex.org/W2613549719","https://openalex.org/W3090755180","https://openalex.org/W3048955117","https://openalex.org/W3016940091"],"abstract_inverted_index":{"Hybrid":[0],"logic":[1],"style":[2],"is":[3,24,42,60],"widely":[4],"used":[5],"to":[6],"implement":[7],"full":[8,46,146],"adder":[9,147],"(FA)":[10],"circuits.":[11],"Performance":[12],"of":[13,18,30,56,88,96,123,127,154,166],"hybrid":[14],"FA":[15],"in":[16,65,101,121,140],"terms":[17,122],"delay,":[19],"power,":[20],"and":[21,109,112,143],"driving":[22,133],"capability":[23],"largely":[25],"dependent":[26],"on":[27],"the":[28,57,77,89,105,132,135,155,159,170],"performance":[29,55,161],"XOR-XNOR":[31,40,91,107],"circuit.":[32],"In":[33],"this":[34,102],"article,":[35],"a":[36,163],"high-speed,":[37],"low-power":[38],"10-T":[39],"circuit":[41,59,75,108],"proposed,":[43],"which":[44],"provides":[45],"swing":[47],"outputs":[48],"simultaneously":[49],"with":[50],"improved":[51],"delay":[52,79],"performance.":[53],"The":[54,73,115],"proposed":[58,74,100,106,116,136,156],"measured":[61],"by":[62,84],"simulating":[63],"it":[64],"cadence":[66],"virtuoso":[67],"environment":[68],"using":[69],"90-nm":[70],"CMOS":[71],"technology.":[72],"reduces":[76],"power":[78],"product":[80],"(PDP)":[81],"at":[82],"least":[83],"7.5%":[85],"than":[86,125],"that":[87,126,152],"available":[90,110],"modules.":[92,114],"Four":[93],"different":[94],"designs":[95],"FAs":[97,117,137,157],"are":[98,138],"also":[99],"article":[103],"utilizing":[104],"sum":[111],"carry":[113],"provide":[118,158],"2%-28.13%":[119],"improvement":[120],"PDP":[124],"other":[128],"architectures.":[129],"To":[130],"measure":[131],"capabilities,":[134],"embedded":[139],"2-,":[141],"4-,":[142],"8-bit":[144],"cascaded":[145],"(CFA)":[148],"structures.":[149],"Results":[150],"show":[151],"two":[153],"best":[160],"for":[162],"higher":[164],"number":[165],"bits":[167],"among":[168],"all":[169],"FAs.":[171]},"counts_by_year":[{"year":2026,"cited_by_count":8},{"year":2025,"cited_by_count":23},{"year":2024,"cited_by_count":29},{"year":2023,"cited_by_count":25},{"year":2022,"cited_by_count":30},{"year":2021,"cited_by_count":14}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}
