{"id":"https://openalex.org/W3016629747","doi":"https://doi.org/10.1109/tvlsi.2020.2983458","title":"Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations","display_name":"Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations","publication_year":2020,"publication_date":"2020-04-15","ids":{"openalex":"https://openalex.org/W3016629747","doi":"https://doi.org/10.1109/tvlsi.2020.2983458","mag":"3016629747"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2020.2983458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2983458","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070455563","display_name":"Amir Fathi","orcid":"https://orcid.org/0000-0001-8420-9909"},"institutions":[{"id":"https://openalex.org/I38476204","display_name":"Urmia University","ror":"https://ror.org/032fk0x53","country_code":"IR","type":"education","lineage":["https://openalex.org/I38476204"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Amir Fathi","raw_affiliation_strings":["Microelectronic Research Laboratory, Urmia University, Urmia, Iran"],"raw_orcid":"https://orcid.org/0000-0001-8420-9909","affiliations":[{"raw_affiliation_string":"Microelectronic Research Laboratory, Urmia University, Urmia, Iran","institution_ids":["https://openalex.org/I38476204"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038836097","display_name":"Behbood Mashoufi","orcid":"https://orcid.org/0000-0002-9472-6069"},"institutions":[{"id":"https://openalex.org/I38476204","display_name":"Urmia University","ror":"https://ror.org/032fk0x53","country_code":"IR","type":"education","lineage":["https://openalex.org/I38476204"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Behbood Mashoufi","raw_affiliation_strings":["Microelectronic Research Laboratory, Urmia University, Urmia, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronic Research Laboratory, Urmia University, Urmia, Iran","institution_ids":["https://openalex.org/I38476204"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033080203","display_name":"Sarkis Azizian","orcid":"https://orcid.org/0000-0002-7820-2601"},"institutions":[{"id":"https://openalex.org/I80543232","display_name":"K.N.Toosi University of Technology","ror":"https://ror.org/0433abe34","country_code":"IR","type":"education","lineage":["https://openalex.org/I80543232"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Sarkis Azizian","raw_affiliation_strings":["Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0002-7820-2601","affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I80543232"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2894,"has_fulltext":false,"cited_by_count":41,"citation_normalized_percentile":{"value":0.88463193,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"28","issue":"6","first_page":"1403","last_page":"1412"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/gas-compressor","display_name":"Gas compressor","score":0.7799798250198364},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6818416118621826},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5737236738204956},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5209044814109802},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5015881061553955},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4990997314453125},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.46702173352241516},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.46441859006881714},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42358073592185974},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4160003662109375},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3274300992488861},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28833284974098206},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11870411038398743}],"concepts":[{"id":"https://openalex.org/C131097465","wikidata":"https://www.wikidata.org/wiki/Q178898","display_name":"Gas compressor","level":2,"score":0.7799798250198364},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6818416118621826},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5737236738204956},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5209044814109802},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5015881061553955},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4990997314453125},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.46702173352241516},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.46441859006881714},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42358073592185974},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4160003662109375},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3274300992488861},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28833284974098206},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11870411038398743},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2020.2983458","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2983458","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7900000214576721,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1480110320","https://openalex.org/W1538622776","https://openalex.org/W2055036380","https://openalex.org/W2058942958","https://openalex.org/W2078966583","https://openalex.org/W2087491408","https://openalex.org/W2093398961","https://openalex.org/W2098621554","https://openalex.org/W2103490953","https://openalex.org/W2107088801","https://openalex.org/W2111016924","https://openalex.org/W2115762596","https://openalex.org/W2127974982","https://openalex.org/W2138968074","https://openalex.org/W2154098113","https://openalex.org/W2168350974","https://openalex.org/W2171262322","https://openalex.org/W2595026691","https://openalex.org/W2784087931","https://openalex.org/W6632167533","https://openalex.org/W6677464167"],"related_works":["https://openalex.org/W4225162125","https://openalex.org/W2413549489","https://openalex.org/W2151908724","https://openalex.org/W2574819041","https://openalex.org/W3004908818","https://openalex.org/W2545536103","https://openalex.org/W2886813482","https://openalex.org/W3084052796","https://openalex.org/W3009767082","https://openalex.org/W2132784251"],"abstract_inverted_index":{"Design":[0],"methodology":[1],"for":[2,49,64,70,82,111,133,169,206],"ultrahigh-speed":[3],"5-2":[4,65,208],"and":[5,37,67,76,103,122,175,186],"7-2":[6,71,217],"compressors":[7,181],"has":[8,23,61,148,203],"been":[9,24,62,92,120,149,204],"illustrated":[10],"in":[11,41,54,79],"this":[12],"article.":[13],"With":[14],"the":[15,20,30,34,47,50,59,87,116,129,134,137,153,156,162,179,195,198,207,211,215],"help":[16],"of":[17,136,155,200,214],"introduced":[18],"procedure,":[19],"gate-level":[21],"delay":[22,199,213],"reduced":[25],"considerably":[26],"when":[27],"compared":[28],"with":[29],"previous":[31,192],"designs,":[32],"while":[33,210],"total":[35],"transistor":[36],"gate":[38],"count":[39],"remain":[40],"a":[42,107,112,141],"reasonable":[43,108],"range.":[44],"By":[45],"starting":[46],"discussion":[48],"carry":[51],"rippling":[52],"problem":[53],"n":[55],"-":[56],"2":[57],"compressors,":[58],"method":[60],"developed":[63],"compressor":[66,158,209,218],"is":[68,219],"expanded":[69],"architecture,":[72],"which":[73],"shows":[74],"32%":[75],"30%":[77],"improvement":[78],"speed":[80,184],"performance":[81,185],"these":[83],"structures,":[84],"respectively.":[85],"Also,":[86],"careful":[88],"design":[89],"considerations":[90],"have":[91,119],"taken":[93],"into":[94],"account":[95],"to":[96,151],"keep":[97],"other":[98],"characteristics,":[99],"such":[100],"as":[101],"power":[102,177],"active,":[104],"are":[105],"at":[106],"level.":[109],"Moreover,":[110],"fair":[113],"comparative":[114],"conclusion,":[115],"best-reported":[117],"circuits":[118],"redesigned,":[121],"their":[123],"parasitic":[124],"elements":[125],"were":[126],"extracted":[127],"utilizing":[128],"same":[130],"technology":[131,174],"employed":[132],"synthesis":[135],"proposed":[138,180],"circuits.":[139],"Finally,":[140],"typical":[142],"16":[143,145],"\u00d7":[144],"bit":[146],"multiplier":[147],"implemented":[150],"investigate":[152],"efficiency":[154],"designed":[157,216],"blocks.":[159],"Based":[160],"on":[161],"postlayout":[163],"simulation":[164],"results":[165,196],"provided":[166],"using":[167],"HSPICE":[168],"TSMC":[170],"0.18-\u03bcm":[171],"standard":[172],"CMOS":[173],"1.8-V":[176],"supply,":[178],"demonstrate":[182],"better":[183],"power-delay":[187],"product":[188],"(PDP)":[189],"factor":[190],"over":[191],"works.":[193],"As":[194],"depict,":[197],"303":[201],"ps":[202],"achieved":[205],"measured":[212],"464":[220],"ps.":[221]},"counts_by_year":[{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}