{"id":"https://openalex.org/W3007797378","doi":"https://doi.org/10.1109/tvlsi.2020.2970041","title":"Approximate Memory Compression","display_name":"Approximate Memory Compression","publication_year":2020,"publication_date":"2020-02-20","ids":{"openalex":"https://openalex.org/W3007797378","doi":"https://doi.org/10.1109/tvlsi.2020.2970041","mag":"3007797378"},"language":"en","primary_location":{"id":"doi:10.1109/tvlsi.2020.2970041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2970041","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047643363","display_name":"Ashish Ranjan","orcid":"https://orcid.org/0000-0003-2434-0475"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]},{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ashish Ranjan","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, Yorktown Heights, USA","School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA"],"raw_orcid":"https://orcid.org/0000-0003-2434-0475","affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066464351","display_name":"Arnab Raha","orcid":"https://orcid.org/0000-0002-8848-1069"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arnab Raha","raw_affiliation_strings":["Intel Corporation, Santa Clara, USA","School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA"],"raw_orcid":"https://orcid.org/0000-0002-8848-1069","affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102009759","display_name":"Vijay Raghunathan","orcid":"https://orcid.org/0000-0003-4713-5386"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijay Raghunathan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA"],"raw_orcid":"https://orcid.org/0000-0003-4713-5386","affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065766721","display_name":"Anand Raghunathan","orcid":"https://orcid.org/0000-0002-4624-564X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anand Raghunathan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.8666,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.94020375,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":93,"max":99},"biblio":{"volume":"28","issue":"4","first_page":"980","last_page":"991"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8165625929832458},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.7404870986938477},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6404252648353577},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.6235897541046143},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.612013041973114},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.5576542615890503},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.547310471534729},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.48535314202308655},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.4462863802909851},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4357690215110779},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.42679280042648315},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42029818892478943},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4069197475910187},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3991566300392151},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.383819043636322}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8165625929832458},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.7404870986938477},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6404252648353577},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.6235897541046143},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.612013041973114},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.5576542615890503},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.547310471534729},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.48535314202308655},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.4462863802909851},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4357690215110779},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.42679280042648315},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42029818892478943},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4069197475910187},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3991566300392151},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.383819043636322},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tvlsi.2020.2970041","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tvlsi.2020.2970041","pdf_url":null,"source":{"id":"https://openalex.org/S37538908","display_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","issn_l":"1063-8210","issn":["1063-8210","1557-9999"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G2984175817","display_name":null,"funder_award_id":"1423290","funder_id":"https://openalex.org/F4320335353","funder_display_name":"National Science Foundation of Sri Lanka"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320335353","display_name":"National Science Foundation of Sri Lanka","ror":"https://ror.org/010xaa060"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":41,"referenced_works":["https://openalex.org/W1851732076","https://openalex.org/W1985148487","https://openalex.org/W1992271541","https://openalex.org/W2003777196","https://openalex.org/W2006198238","https://openalex.org/W2020517863","https://openalex.org/W2025632321","https://openalex.org/W2026005150","https://openalex.org/W2030922317","https://openalex.org/W2041420601","https://openalex.org/W2046531456","https://openalex.org/W2052201685","https://openalex.org/W2053709612","https://openalex.org/W2060204338","https://openalex.org/W2091434413","https://openalex.org/W2097243222","https://openalex.org/W2112197601","https://openalex.org/W2122636510","https://openalex.org/W2131017271","https://openalex.org/W2131413854","https://openalex.org/W2147657366","https://openalex.org/W2147926533","https://openalex.org/W2171894735","https://openalex.org/W2231875869","https://openalex.org/W2237415205","https://openalex.org/W2244005500","https://openalex.org/W2293281321","https://openalex.org/W2474451066","https://openalex.org/W2562506265","https://openalex.org/W2565435739","https://openalex.org/W2567051523","https://openalex.org/W2593172471","https://openalex.org/W2612832886","https://openalex.org/W2742847738","https://openalex.org/W2743069335","https://openalex.org/W4236372686","https://openalex.org/W4248591063","https://openalex.org/W4249176607","https://openalex.org/W4313016175","https://openalex.org/W6648637463","https://openalex.org/W6737322433"],"related_works":["https://openalex.org/W2155373950","https://openalex.org/W2753615087","https://openalex.org/W2587873888","https://openalex.org/W4243618206","https://openalex.org/W4243576563","https://openalex.org/W2782503170","https://openalex.org/W2069490402","https://openalex.org/W1991896026","https://openalex.org/W3170849636","https://openalex.org/W2047684617"],"abstract_inverted_index":{"Memory":[0],"subsystems":[1],"are":[2,158],"a":[3,24,122,178,202,226,238,244,253,283],"major":[4],"energy":[5,48,269],"bottleneck":[6],"in":[7,68,110,198,266,286],"computing":[8,204],"platforms":[9],"due":[10],"to":[11,41,61,74,81,121,134,149,152,160,192],"frequent":[12],"transfers":[13],"between":[14],"processors":[15],"and":[16,38,49,209,235,243,278,282,297],"off-chip":[17,43],"memory.":[18],"We":[19,51,185],"propose":[20],"approximate":[21,53,65,92,141,260],"memory":[22,44,54,59,66,69,93,116,119,130,142,196,233,261,268],"compression,":[23],"technique":[25],"that":[26,70,106,125,157,177],"leverages":[27],"the":[28,58,78,103,135,169,173,199,217,220,230],"intrinsic":[29],"resilience":[30],"of":[31,64,201,219,256],"emerging":[32],"workloads":[33],"such":[34,101,176],"as":[35,102],"machine":[36,257],"learning":[37,258],"data":[39,79,112,154],"analytics":[40],"reduce":[42],"traffic,":[45,131],"thereby":[46,128],"improving":[47],"performance.":[50],"realize":[52],"compression":[55,123,262],"by":[56,189],"enhancing":[57],"controller":[60,117,234],"be":[62,108],"aware":[63],"regions-regions":[67],"contain":[71],"approximation-resilient":[72],"data-and":[73],"transparently":[75],"compress":[76],"(decompress)":[77],"written":[80],"(read":[82],"from)":[83],"these":[84],"regions.":[85],"To":[86,215],"provide":[87],"control":[88,165],"over":[89],"approximations,":[90,127],"each":[91,111,140],"region":[94],"is":[95,147,183],"associated":[96],"with":[97,301],"an":[98],"error":[99,105,137,170],"constraint":[100,138],"maximum":[104],"may":[107],"introduced":[109],"element.":[113],"The":[114],"quality-aware":[115],"subjects":[118],"transactions":[120],"scheme":[124],"introduces":[126],"reducing":[129],"while":[132],"adhering":[133],"specified":[136],"for":[139,172,271,275,280,290,294,299],"region.":[143],"A":[144,162],"software":[145],"interface":[146],"provided":[148],"allow":[150],"programmers":[151],"identify":[153],"structures":[155],"(DSs)":[156],"resilient":[159],"approximations.":[161],"runtime":[163],"quality":[164,182],"framework":[166],"automatically":[167],"determines":[168],"constraints":[171],"identified":[174],"DSs":[175],"given":[179],"target":[180],"application-level":[181],"maintained.":[184],"evaluate":[186],"our":[187],"proposal":[188],"applying":[190],"it":[191],"three":[193],"different":[194],"main":[195,267],"technologies":[197],"context":[200],"general-purpose":[203],"system-DDR3":[205],"DRAM,":[206,208,273,277,292,296],"LPDDR3":[207,276,295],"spin-transfer":[210],"torque":[211],"magnetic":[212],"RAM":[213],"(STT-MRAM).":[214],"demonstrate":[216],"feasibility":[218],"proposed":[221],"concepts,":[222],"we":[223],"also":[224],"implement":[225],"hardware":[227],"prototype":[228],"using":[229],"Intel":[231],"UniPHY-DDR3":[232],"Nios-II":[236],"processor,":[237],"Hynix":[239],"DDR3":[240,272,291],"DRAM":[241],"module,":[242],"Stratix-IV":[245],"field-programmable":[246],"gate":[247],"array":[248],"(FPGA)":[249],"development":[250],"board.":[251],"Across":[252],"wide":[254],"range":[255],"benchmarks,":[259],"obtains":[263],"significant":[264],"benefits":[265],"(1.18\u00d7":[270],"1.52\u00d7":[274],"2.0\u00d7":[279],"STT-MRAM)":[281,300],"simultaneous":[284],"improvement":[285],"execution":[287],"time":[288],"(5.2%":[289],"5.4%":[293],"9.3%":[298],"nearly":[302],"identical":[303],"application":[304],"output":[305],"quality.":[306]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":6},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}